1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004, 2011 Freescale Semiconductor.
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
12 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <fsl_ddr_sdram.h>
17 #include <spd_sdram.h>
18 #include <linux/delay.h>
19 #include <linux/libfdt.h>
20 #include <fdt_support.h>
22 #include "../common/cadmus.h"
23 #include "../common/eeprom.h"
24 #include "../common/via.h"
26 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
27 extern void ddr_enable_ecc(unsigned int dram_size);
30 void local_bus_init(void);
33 * I/O Port configuration table
35 * if conf is 1, then that port pin will be configured at boot time
36 * according to the five values podr/pdir/ppar/psor/pdat for that entry
39 const iop_conf_t iop_conf_tab[4][32] = {
41 /* Port A configuration */
42 { /* conf ppar psor pdir podr pdat */
43 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
44 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
45 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
46 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
47 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
48 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
49 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
50 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
51 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
52 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
53 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
54 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
55 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
56 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
57 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
58 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
59 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
60 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
61 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
62 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
63 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
64 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
65 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
66 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
67 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
68 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
69 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
70 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
71 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
72 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
73 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
74 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
77 /* Port B configuration */
78 { /* conf ppar psor pdir podr pdat */
79 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
80 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
81 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
82 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
83 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
84 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
85 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
86 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
87 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
88 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
89 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
90 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
91 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
92 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
93 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
94 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
95 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
96 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
97 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
98 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
99 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
100 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
101 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
102 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
103 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
104 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
105 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
106 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
107 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
108 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
109 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
110 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
114 { /* conf ppar psor pdir podr pdat */
115 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
116 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
117 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
118 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
119 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
120 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
121 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
122 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
123 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
124 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
125 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
126 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
127 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
128 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
129 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
130 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
131 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
132 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
133 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
134 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
135 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
136 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
137 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
138 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
139 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
140 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
141 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
142 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
143 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
144 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
145 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
146 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
150 { /* conf ppar psor pdir podr pdat */
151 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
152 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
153 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
154 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
155 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
156 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
157 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
158 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
159 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
160 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
161 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
162 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
163 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
164 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
165 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
166 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
167 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
168 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
169 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
170 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
171 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
172 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
173 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
174 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
175 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
176 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
177 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
178 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
179 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
180 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
181 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
182 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
186 int checkboard (void)
188 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
191 /* PCI slot in USER bits CSR[6:7] by convention. */
192 uint pci_slot = get_pci_slot ();
194 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
195 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
196 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
197 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
199 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
201 uint cpu_board_rev = get_cpu_board_revision ();
203 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
204 get_board_version (), pci_slot);
206 printf ("CPU Board Revision %d.%d (0x%04x)\n",
207 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
208 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
210 printf("PCI1: %d bit, %s MHz, %s\n",
212 strmhz(buf, pci1_speed),
213 pci1_clk_sel ? "sync" : "async");
216 printf("PCI2: 32 bit, 66 MHz, %s\n",
217 pci2_clk_sel ? "sync" : "async");
219 printf("PCI2: disabled\n");
223 * Initialize local bus.
231 * Initialize Local Bus
236 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
237 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
246 * Fix Local Bus clock glitch when DLL is enabled.
248 * If localbus freq is < 66MHz, DLL bypass mode must be used.
249 * If localbus freq is > 133MHz, DLL can be safely enabled.
250 * Between 66 and 133, the DLL is enabled with an override workaround.
253 get_sys_info(&sysinfo);
254 clkdiv = lbc->lcrr & LCRR_CLKDIV;
255 lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
258 lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
260 } else if (lbc_hz >= 133) {
261 lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
264 lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
268 * Sample LBC DLL ctrl reg, upshift it to set the
271 temp_lbcdll = gur->lbcdllcr;
272 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
273 asm("sync;isync;msync");
278 * Initialize SDRAM memory on the Local Bus.
280 void lbc_sdram_init(void)
282 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
285 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
286 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
291 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
295 * Setup SDRAM Base and Option Registers
297 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
298 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
299 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
302 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
303 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
307 * Determine which address lines to use baed on CPU board rev.
309 cpu_board_rev = get_cpu_board_revision();
310 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
311 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
312 lsdmr_common |= LSDMR_BSMA1617;
313 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
314 lsdmr_common |= LSDMR_BSMA1516;
317 * Assume something unable to identify itself is
318 * really old, and likely has lines 16/17 mapped.
320 lsdmr_common |= LSDMR_BSMA1617;
324 * Issue PRECHARGE ALL command.
326 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
329 ppcDcbf((unsigned long) sdram_addr);
333 * Issue 8 AUTO REFRESH commands.
335 for (idx = 0; idx < 8; idx++) {
336 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
339 ppcDcbf((unsigned long) sdram_addr);
344 * Issue 8 MODE-set command.
346 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
349 ppcDcbf((unsigned long) sdram_addr);
353 * Issue NORMAL OP command.
355 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
358 ppcDcbf((unsigned long) sdram_addr);
359 udelay(200); /* Overkill. Must wait > 200 bus cycles */
361 #endif /* enable SDRAM init */
364 #if defined(CONFIG_PCI)
365 /* For some reason the Tundra PCI bridge shows up on itself as a
366 * different device. Work around that by refusing to configure it.
368 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
370 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
371 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
372 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
373 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
374 mpc85xx_config_via_usbide, {0,0,0}},
375 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
376 mpc85xx_config_via_usb, {0,0,0}},
377 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
378 mpc85xx_config_via_usb2, {0,0,0}},
379 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
380 mpc85xx_config_via_power, {0,0,0}},
381 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
382 mpc85xx_config_via_ac97, {0,0,0}},
386 static struct pci_controller hose[] = {
387 { config_table: pci_mpc85xxcds_config_table,},
388 #ifdef CONFIG_MPC85XX_PCI2
393 #endif /* CONFIG_PCI */
399 pci_mpc85xx_init(hose);
403 #if defined(CONFIG_OF_BOARD_SETUP)
405 ft_pci_setup(void *blob, bd_t *bd)
410 node = fdt_path_offset(blob, "/aliases");
414 path = fdt_getprop(blob, node, "pci0", NULL);
416 tmp[1] = hose[0].last_busno - hose[0].first_busno;
417 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
420 #ifdef CONFIG_MPC85XX_PCI2
421 path = fdt_getprop(blob, node, "pci1", NULL);
423 tmp[1] = hose[1].last_busno - hose[1].first_busno;
424 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);