1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
12 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_pci.h>
17 #include <fsl_ddr_sdram.h>
19 #include <asm/fsl_serdes.h>
22 #include <linux/libfdt.h>
23 #include <spd_sdram.h>
24 #include <fdt_support.h>
30 #include "../common/sgmii_riser.h"
32 int board_early_init_f (void)
35 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
37 setbits_be32(&gur->pmuxcr,
38 (MPC85xx_PMUXCR_SDHC_CD |
39 MPC85xx_PMUXCR_SDHC_WP));
41 /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
42 * however, this erratum only applies to MPC8536 Rev1.0.
43 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
44 if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
45 (SVR_MIN(get_svr()) >= 0x1))
46 || (SVR_MAJ(get_svr() & 0x7) > 0x1))
47 setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
55 u8 *pixis_base = (u8 *)PIXIS_BASE;
57 printf("Board: MPC8536DS Sys ID: 0x%02x, "
58 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
59 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
60 in_8(pixis_base + PIXIS_PVER));
62 vboot = in_8(pixis_base + PIXIS_VBOOT);
63 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
64 case PIXIS_VBOOT_LBMAP_NOR0:
67 case PIXIS_VBOOT_LBMAP_NOR1:
70 case PIXIS_VBOOT_LBMAP_NOR2:
73 case PIXIS_VBOOT_LBMAP_NOR3:
76 case PIXIS_VBOOT_LBMAP_PJET:
79 case PIXIS_VBOOT_LBMAP_NAND:
87 #if !defined(CONFIG_SPD_EEPROM)
89 * Fixed sdram init -- doesn't use serial presence detect.
92 phys_size_t fixed_sdram (void)
94 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
95 struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
98 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
99 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
101 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
102 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
103 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
104 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
105 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
106 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
107 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
108 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
109 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
110 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
112 #if defined (CONFIG_DDR_ECC)
113 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
114 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
115 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
121 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
123 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
125 debug("DDR - 1st controller: memory initializing\n");
127 * Poll until memory is initialized.
128 * 512 Meg at 400 might hit this 200 times or so.
130 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
133 debug("DDR: memory initialized\n\n");
138 return 512 * 1024 * 1024;
144 static struct pci_controller pci1_hose;
148 void pci_init_board(void)
150 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
151 struct fsl_pci_info pci_info;
152 u32 devdisr, pordevsr;
153 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
154 int first_free_busno;
156 first_free_busno = fsl_pcie_init_board(0);
159 devdisr = in_be32(&gur->devdisr);
160 pordevsr = in_be32(&gur->pordevsr);
161 porpllsr = in_be32(&gur->porpllsr);
163 pci_speed = 66666000;
165 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
166 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
168 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
169 SET_STD_PCI_INFO(pci_info, 1);
170 set_next_law(pci_info.mem_phys,
171 law_size_bits(pci_info.mem_size), pci_info.law);
172 set_next_law(pci_info.io_phys,
173 law_size_bits(pci_info.io_size), pci_info.law);
175 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
176 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
178 (pci_speed == 33333000) ? "33" :
179 (pci_speed == 66666000) ? "66" : "unknown",
180 pci_clk_sel ? "sync" : "async",
181 pci_agent ? "agent" : "host",
182 pci_arb ? "arbiter" : "external-arbiter",
185 first_free_busno = fsl_pci_init_port(&pci_info,
186 &pci1_hose, first_free_busno);
188 printf("PCI: disabled\n");
193 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
198 int board_early_init_r(void)
200 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
201 int flash_esel = find_tlb_idx((void *)flashbase, 1);
204 * Remap Boot flash + PROMJET region to caching-inhibited
205 * so that flash can be erased properly.
208 /* Flush d-cache and invalidate i-cache of any FLASH data */
212 if (flash_esel == -1) {
213 /* very unlikely unless something is messed up */
214 puts("Error: Could not find TLB for FLASH BASE\n");
215 flash_esel = 1; /* give our best effort to continue */
217 /* invalidate existing TLB entry for flash + promjet */
218 disable_tlb(flash_esel);
221 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
222 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
223 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
228 int board_eth_init(bd_t *bis)
230 #ifdef CONFIG_TSEC_ENET
231 struct fsl_pq_mdio_info mdio_info;
232 struct tsec_info_struct tsec_info[2];
236 SET_STD_TSEC_INFO(tsec_info[num], 1);
237 if (is_serdes_configured(SGMII_TSEC1)) {
238 puts("eTSEC1 is in sgmii mode.\n");
239 tsec_info[num].phyaddr = 0;
240 tsec_info[num].flags |= TSEC_SGMII;
245 SET_STD_TSEC_INFO(tsec_info[num], 3);
246 if (is_serdes_configured(SGMII_TSEC3)) {
247 puts("eTSEC3 is in sgmii mode.\n");
248 tsec_info[num].phyaddr = 1;
249 tsec_info[num].flags |= TSEC_SGMII;
255 printf("No TSECs initialized\n");
259 #ifdef CONFIG_FSL_SGMII_RISER
260 if (is_serdes_configured(SGMII_TSEC1) ||
261 is_serdes_configured(SGMII_TSEC3)) {
262 fsl_sgmii_riser_init(tsec_info, num);
266 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
267 mdio_info.name = DEFAULT_MII_NAME;
268 fsl_pq_mdio_init(bis, &mdio_info);
270 tsec_eth_init(bis, tsec_info, num);
272 return pci_eth_init(bis);
275 #if defined(CONFIG_OF_BOARD_SETUP)
276 int ft_board_setup(void *blob, bd_t *bd)
278 ft_cpu_setup(blob, bd);
282 #ifdef CONFIG_FSL_SGMII_RISER
283 fsl_sgmii_riser_fdt_fixup(blob);
286 #ifdef CONFIG_HAS_FSL_MPH_USB
287 fsl_fdt_fixup_dr_usb(blob, bd);