board/freescale/mpc837xerdb/mpc837xerdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <env.h>
  10 #include <hwconfig.h>
  11 #include <i2c.h>
  12 #include <init.h>
  13 #include <asm/io.h>
  14 #include <asm/fsl_mpc83xx_serdes.h>
  15 #include <fdt_support.h>
  16 #include <spd_sdram.h>
  17 #include <vsc7385.h>
  18 #include <fsl_esdhc.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #if defined(CONFIG_SYS_DRAM_TEST)
  23 int
  24 testdram(void)
  25 {
  26         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  27         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  28         uint *p;
  29
  30         printf("Testing DRAM from 0x%08x to 0x%08x\n",
  31                CONFIG_SYS_MEMTEST_START,
  32                CONFIG_SYS_MEMTEST_END);
  33
  34         printf("DRAM test phase 1:\n");
  35         for (p = pstart; p < pend; p++)
  36                 *p = 0xaaaaaaaa;
  37
  38         for (p = pstart; p < pend; p++) {
  39                 if (*p != 0xaaaaaaaa) {
  40                         printf("DRAM test fails at: %08x\n", (uint) p);
  41                         return 1;
  42                 }
  43         }
  44
  45         printf("DRAM test phase 2:\n");
  46         for (p = pstart; p < pend; p++)
  47                 *p = 0x55555555;
  48
  49         for (p = pstart; p < pend; p++) {
  50                 if (*p != 0x55555555) {
  51                         printf("DRAM test fails at: %08x\n", (uint) p);
  52                         return 1;
  53                 }
  54         }
  55
  56         printf("DRAM test passed.\n");
  57         return 0;
  58 }
  59 #endif
  60
  61 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  62 void ddr_enable_ecc(unsigned int dram_size);
  63 #endif
  64 int fixed_sdram(void);
  65
  66 int dram_init(void)
  67 {
  68         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  69         u32 msize = 0;
  70
  71         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  72                 return -ENXIO;
  73
  74 #if defined(CONFIG_SPD_EEPROM)
  75         msize = spd_sdram();
  76 #else
  77         msize = fixed_sdram();
  78 #endif
  79
  80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  81         /* Initialize DDR ECC byte */
  82         ddr_enable_ecc(msize * 1024 * 1024);
  83 #endif
  84         /* return total bus DDR size(bytes) */
  85         gd->ram_size = msize * 1024 * 1024;
  86
  87         return 0;
  88 }
  89
  90 #if !defined(CONFIG_SPD_EEPROM)
  91 /*************************************************************************
  92  *  fixed sdram init -- doesn't use serial presence detect.
  93  ************************************************************************/
  94 int fixed_sdram(void)
  95 {
  96         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  97         u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  98         u32 msize_log2 = __ilog2(msize);
  99
 100         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 101         im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 102
 103         im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 104         udelay(50000);
 105
 106         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
 107         udelay(1000);
 108
 109         im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
 110         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 111         udelay(1000);
 112
 113         im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 114         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 115         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 116         im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 117         im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 118         im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 119         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 120         im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 121         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 122         sync();
 123         udelay(1000);
 124
 125         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 126         udelay(2000);
 127         return CONFIG_SYS_DDR_SIZE;
 128 }
 129 #endif  /*!CONFIG_SYS_SPD_EEPROM */
 130
 131 int checkboard(void)
 132 {
 133         puts("Board: Freescale MPC837xERDB\n");
 134         return 0;
 135 }
 136
 137 int board_early_init_f(void)
 138 {
 139 #ifdef CONFIG_FSL_SERDES
 140         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 141         u32 spridr = in_be32(&immr->sysconf.spridr);
 142
 143         /* we check only part num, and don't look for CPU revisions */
 144         switch (PARTID_NO_E(spridr)) {
 145         case SPR_8377:
 146                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 147                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 148                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 149                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 150                 break;
 151         case SPR_8378:
 152                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 153                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 154                 break;
 155         case SPR_8379:
 156                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 157                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 158                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
 159                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 160                 break;
 161         default:
 162                 printf("serdes not configured: unknown CPU part number: "
 163                        "%04x\n", spridr >> 16);
 164                 break;
 165         }
 166 #endif /* CONFIG_FSL_SERDES */
 167         return 0;
 168 }
 169
 170 #ifdef CONFIG_FSL_ESDHC
 171 int board_mmc_init(bd_t *bd)
 172 {
 173         struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
 174         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
 175         int esdhc_hwconfig_enabled = 0;
 176
 177         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
 178                 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
 179
 180         if (esdhc_hwconfig_enabled == 0)
 181                 return 0;
 182
 183         clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
 184         clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
 185
 186         return fsl_esdhc_mmc_init(bd);
 187 }
 188 #endif
 189
 190 /*
 191  * Miscellaneous late-boot configurations
 192  *
 193  * If a VSC7385 microcode image is present, then upload it.
 194 */
 195 int misc_init_r(void)
 196 {
 197         int rc = 0;
 198
 199 #ifdef CONFIG_VSC7385_IMAGE
 200         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 201                 CONFIG_VSC7385_IMAGE_SIZE)) {
 202                 puts("Failure uploading VSC7385 microcode.\n");
 203                 rc = 1;
 204         }
 205 #endif
 206
 207         return rc;
 208 }
 209
 210 #if defined(CONFIG_OF_BOARD_SETUP)
 211
 212 int ft_board_setup(void *blob, bd_t *bd)
 213 {
 214 #ifdef CONFIG_PCI
 215         ft_pci_setup(blob, bd);
 216 #endif
 217         ft_cpu_setup(blob, bd);
 218         fsl_fdt_fixup_dr_usb(blob, bd);
 219         fdt_fixup_esdhc(blob, bd);
 220
 221         return 0;
 222 }
 223 #endif /* CONFIG_OF_BOARD_SETUP */