board/freescale/mpc837xerdb/mpc837xerdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <env.h>
  10 #include <hwconfig.h>
  11 #include <i2c.h>
  12 #include <init.h>
  13 #include <asm/io.h>
  14 #include <asm/fsl_mpc83xx_serdes.h>
  15 #include <fdt_support.h>
  16 #include <spd_sdram.h>
  17 #include <vsc7385.h>
  18 #include <fsl_esdhc.h>
  19 #include <linux/delay.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #if defined(CONFIG_SYS_DRAM_TEST)
  24 int
  25 testdram(void)
  26 {
  27         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  28         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  29         uint *p;
  30
  31         printf("Testing DRAM from 0x%08x to 0x%08x\n",
  32                CONFIG_SYS_MEMTEST_START,
  33                CONFIG_SYS_MEMTEST_END);
  34
  35         printf("DRAM test phase 1:\n");
  36         for (p = pstart; p < pend; p++)
  37                 *p = 0xaaaaaaaa;
  38
  39         for (p = pstart; p < pend; p++) {
  40                 if (*p != 0xaaaaaaaa) {
  41                         printf("DRAM test fails at: %08x\n", (uint) p);
  42                         return 1;
  43                 }
  44         }
  45
  46         printf("DRAM test phase 2:\n");
  47         for (p = pstart; p < pend; p++)
  48                 *p = 0x55555555;
  49
  50         for (p = pstart; p < pend; p++) {
  51                 if (*p != 0x55555555) {
  52                         printf("DRAM test fails at: %08x\n", (uint) p);
  53                         return 1;
  54                 }
  55         }
  56
  57         printf("DRAM test passed.\n");
  58         return 0;
  59 }
  60 #endif
  61
  62 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  63 void ddr_enable_ecc(unsigned int dram_size);
  64 #endif
  65 int fixed_sdram(void);
  66
  67 int dram_init(void)
  68 {
  69         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  70         u32 msize = 0;
  71
  72         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  73                 return -ENXIO;
  74
  75 #if defined(CONFIG_SPD_EEPROM)
  76         msize = spd_sdram();
  77 #else
  78         msize = fixed_sdram();
  79 #endif
  80
  81 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  82         /* Initialize DDR ECC byte */
  83         ddr_enable_ecc(msize * 1024 * 1024);
  84 #endif
  85         /* return total bus DDR size(bytes) */
  86         gd->ram_size = msize * 1024 * 1024;
  87
  88         return 0;
  89 }
  90
  91 #if !defined(CONFIG_SPD_EEPROM)
  92 /*************************************************************************
  93  *  fixed sdram init -- doesn't use serial presence detect.
  94  ************************************************************************/
  95 int fixed_sdram(void)
  96 {
  97         immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  98         u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  99         u32 msize_log2 = __ilog2(msize);
 100
 101         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 102         im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 103
 104         im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 105         udelay(50000);
 106
 107         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
 108         udelay(1000);
 109
 110         im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
 111         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 112         udelay(1000);
 113
 114         im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 115         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 116         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 117         im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 118         im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 119         im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 120         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 121         im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 122         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 123         sync();
 124         udelay(1000);
 125
 126         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 127         udelay(2000);
 128         return CONFIG_SYS_DDR_SIZE;
 129 }
 130 #endif  /*!CONFIG_SYS_SPD_EEPROM */
 131
 132 int checkboard(void)
 133 {
 134         puts("Board: Freescale MPC837xERDB\n");
 135         return 0;
 136 }
 137
 138 int board_early_init_f(void)
 139 {
 140 #ifdef CONFIG_FSL_SERDES
 141         immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 142         u32 spridr = in_be32(&immr->sysconf.spridr);
 143
 144         /* we check only part num, and don't look for CPU revisions */
 145         switch (PARTID_NO_E(spridr)) {
 146         case SPR_8377:
 147                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 148                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 149                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 150                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 151                 break;
 152         case SPR_8378:
 153                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
 154                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 155                 break;
 156         case SPR_8379:
 157                 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
 158                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 159                 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
 160                                  FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 161                 break;
 162         default:
 163                 printf("serdes not configured: unknown CPU part number: "
 164                        "%04x\n", spridr >> 16);
 165                 break;
 166         }
 167 #endif /* CONFIG_FSL_SERDES */
 168         return 0;
 169 }
 170
 171 #ifdef CONFIG_FSL_ESDHC
 172 int board_mmc_init(bd_t *bd)
 173 {
 174         struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
 175         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
 176         int esdhc_hwconfig_enabled = 0;
 177
 178         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
 179                 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
 180
 181         if (esdhc_hwconfig_enabled == 0)
 182                 return 0;
 183
 184         clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
 185         clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
 186
 187         return fsl_esdhc_mmc_init(bd);
 188 }
 189 #endif
 190
 191 /*
 192  * Miscellaneous late-boot configurations
 193  *
 194  * If a VSC7385 microcode image is present, then upload it.
 195 */
 196 int misc_init_r(void)
 197 {
 198         int rc = 0;
 199
 200 #ifdef CONFIG_VSC7385_IMAGE
 201         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 202                 CONFIG_VSC7385_IMAGE_SIZE)) {
 203                 puts("Failure uploading VSC7385 microcode.\n");
 204                 rc = 1;
 205         }
 206 #endif
 207
 208         return rc;
 209 }
 210
 211 #if defined(CONFIG_OF_BOARD_SETUP)
 212
 213 int ft_board_setup(void *blob, bd_t *bd)
 214 {
 215 #ifdef CONFIG_PCI
 216         ft_pci_setup(blob, bd);
 217 #endif
 218         ft_cpu_setup(blob, bd);
 219         fsl_fdt_fixup_dr_usb(blob, bd);
 220         fdt_fixup_esdhc(blob, bd);
 221
 222         return 0;
 223 }
 224 #endif /* CONFIG_OF_BOARD_SETUP */