1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
13 #include <asm/fsl_mpc83xx_serdes.h>
14 #include <spd_sdram.h>
16 #include <linux/delay.h>
17 #include <linux/libfdt.h>
18 #include <fdt_support.h>
19 #include <fsl_esdhc.h>
23 #include "../common/pq-mds-pib.h"
25 DECLARE_GLOBAL_DATA_PTR;
27 int board_early_init_f(void)
29 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
31 /* Enable flash write */
33 /* Clear all of the interrupt of BCSR */
36 #ifdef CONFIG_FSL_SERDES
37 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
38 u32 spridr = in_be32(&immr->sysconf.spridr);
40 /* we check only part num, and don't look for CPU revisions */
41 switch (PARTID_NO_E(spridr)) {
43 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
44 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
47 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
48 FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
51 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
52 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
53 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
54 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
57 printf("serdes not configured: unknown CPU part number: "
58 "%04x\n", spridr >> 16);
61 #endif /* CONFIG_FSL_SERDES */
65 #ifdef CONFIG_FSL_ESDHC
66 int board_mmc_init(bd_t *bd)
68 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
69 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
71 if (!hwconfig("esdhc"))
74 /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
77 /* Set proper bits in SICR to allow SD signals through */
78 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
79 clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
80 SICRH_GPIO2_E_SD | SICRH_SPI_SD);
82 return fsl_esdhc_mmc_init(bd);
86 #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
87 int board_eth_init(bd_t *bd)
89 struct fsl_pq_mdio_info mdio_info;
90 struct tsec_info_struct tsec_info[2];
91 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
92 u32 rcwh = in_be32(&im->reset.rcwh);
96 /* New line after Net: */
100 SET_STD_TSEC_INFO(tsec_info[num], 1);
102 printf(CONFIG_TSEC1_NAME ": ");
104 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
105 if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
107 /* this is default, no need to fixup */
108 } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
110 tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
111 tsec_info[num].flags = TSEC_GIGABIT;
113 printf("unsupported PHY type\n");
118 SET_STD_TSEC_INFO(tsec_info[num], 2);
120 printf(CONFIG_TSEC2_NAME ": ");
122 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
123 if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
125 /* this is default, no need to fixup */
126 } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
128 tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
129 tsec_info[num].flags = TSEC_GIGABIT;
131 printf("unsupported PHY type\n");
136 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
137 mdio_info.name = DEFAULT_MII_NAME;
138 fsl_pq_mdio_init(bd, &mdio_info);
140 return tsec_eth_init(bd, tsec_info, num);
143 static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
150 off = fdt_path_offset(blob, alias);
152 printf("WARNING: could not find %s alias: %s.\n", alias,
157 err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
160 printf("WARNING: could not set phy-connection-type for %s: "
161 "%s.\n", alias, fdt_strerror(err));
165 ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
167 printf("WARNING: could not get phy-handle for %s.\n",
172 off = fdt_node_offset_by_phandle(blob, *ph);
174 printf("WARNING: could not get phy node for %s: %s\n", alias,
179 phy_addr = cpu_to_fdt32(phy_addr);
180 err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
182 printf("WARNING: could not set phy node's reg for %s: "
183 "%s.\n", alias, fdt_strerror(err));
188 static void ft_tsec_fixup(void *blob, bd_t *bd)
190 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
191 u32 rcwh = in_be32(&im->reset.rcwh);
195 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
196 if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
197 __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
201 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
202 if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
203 __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
207 static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
208 #endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
210 int board_early_init_r(void)
212 #ifdef CONFIG_PQ_MDS_PIB
218 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
219 extern void ddr_enable_ecc(unsigned int dram_size);
221 int fixed_sdram(void);
225 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
228 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
231 #if defined(CONFIG_SPD_EEPROM)
234 msize = fixed_sdram();
237 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
238 /* Initialize DDR ECC byte */
239 ddr_enable_ecc(msize * 1024 * 1024);
242 /* return total bus DDR size(bytes) */
243 gd->ram_size = msize * 1024 * 1024;
248 #if !defined(CONFIG_SPD_EEPROM)
249 /*************************************************************************
250 * fixed sdram init -- doesn't use serial presence detect.
251 ************************************************************************/
252 int fixed_sdram(void)
254 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
255 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
256 u32 msize_log2 = __ilog2(msize);
258 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
259 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
261 #if (CONFIG_SYS_DDR_SIZE != 512)
262 #warning Currenly any ddr size other than 512 is not supported
264 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
267 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
270 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
271 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
274 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
275 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
276 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
277 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
278 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
279 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
280 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
281 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
282 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
283 __asm__ __volatile__("sync");
286 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
288 return CONFIG_SYS_DDR_SIZE;
290 #endif /*!CONFIG_SYS_SPD_EEPROM */
294 puts("Board: Freescale MPC837xEMDS\n");
299 int board_pci_host_broken(void)
301 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
302 const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
304 /* It's always OK in case of external arbiter. */
305 if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
308 if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
314 static void ft_pci_fixup(void *blob, bd_t *bd)
316 const char *status = "broken (no arbiter)";
320 off = fdt_path_offset(blob, "pci0");
322 printf("WARNING: could not find pci0 alias: %s.\n",
327 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
329 printf("WARNING: could not set status for pci0: %s.\n",
336 #if defined(CONFIG_OF_BOARD_SETUP)
337 int ft_board_setup(void *blob, bd_t *bd)
339 ft_cpu_setup(blob, bd);
340 ft_tsec_fixup(blob, bd);
341 fsl_fdt_fixup_dr_usb(blob, bd);
342 fdt_fixup_esdhc(blob, bd);
344 ft_pci_setup(blob, bd);
345 if (board_pci_host_broken())
346 ft_pci_fixup(blob, bd);
347 ft_pcie_fixup(blob, bd);
352 #endif /* CONFIG_OF_BOARD_SETUP */