board/freescale/mpc8349itx/mpc8349itx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  */
   5
   6 #include <common.h>
   7 #include <fdt_support.h>
   8 #include <init.h>
   9 #include <ioports.h>
  10 #include <log.h>
  11 #include <mpc83xx.h>
  12 #include <i2c.h>
  13 #include <miiphy.h>
  14 #include <vsc7385.h>
  15 #ifdef CONFIG_PCI
  16 #include <asm/mpc8349_pci.h>
  17 #include <pci.h>
  18 #endif
  19 #include <spd_sdram.h>
  20 #include <asm/mmu.h>
  21 #if defined(CONFIG_OF_LIBFDT)
  22 #include <linux/libfdt.h>
  23 #endif
  24
  25 #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
  26 #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #ifndef CONFIG_SPD_EEPROM
  31 /*************************************************************************
  32  *  fixed sdram init -- doesn't use serial presence detect.
  33  ************************************************************************/
  34 int fixed_sdram(void)
  35 {
  36         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  37         /* The size of RAM, in bytes */
  38         u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
  39         u32 ddr_size_log2 = __ilog2(ddr_size);
  40
  41         im->sysconf.ddrlaw[0].ar =
  42             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  43         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  44
  45 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  46 #warning Chip select bounds is only configurable in 16MB increments
  47 #endif
  48         im->ddr.csbnds[0].csbnds =
  49                 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  50                 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  51                                 CSBNDS_EA_SHIFT) & CSBNDS_EA);
  52         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  53
  54         /* Only one CS for DDR */
  55         im->ddr.cs_config[1] = 0;
  56         im->ddr.cs_config[2] = 0;
  57         im->ddr.cs_config[3] = 0;
  58
  59         debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
  60         debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
  61
  62         debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
  63         debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
  64
  65         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  66         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
  67         im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
  68         im->ddr.sdram_mode =
  69             (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
  70         im->ddr.sdram_interval =
  71             (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
  72                                                        SDRAM_INTERVAL_BSTOPRE_SHIFT);
  73         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  74
  75         udelay(200);
  76
  77         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  78
  79         debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
  80         debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
  81         debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
  82         debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
  83         debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
  84
  85         return CONFIG_SYS_DDR_SIZE;
  86 }
  87 #endif
  88
  89 #ifdef CONFIG_PCI
  90 /*
  91  * Initialize PCI Devices, report devices found
  92  */
  93 #ifndef CONFIG_PCI_PNP
  94 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
  95         {
  96          PCI_ANY_ID,
  97          PCI_ANY_ID,
  98          PCI_ANY_ID,
  99          PCI_ANY_ID,
 100          0x0f,
 101          PCI_ANY_ID,
 102          pci_cfgfunc_config_device,
 103          {
 104           PCI_ENET0_IOADDR,
 105           PCI_ENET0_MEMADDR,
 106           PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
 107          },
 108         {}
 109 }
 110 #endif
 111
 112 volatile static struct pci_controller hose[] = {
 113         {
 114 #ifndef CONFIG_PCI_PNP
 115               config_table:pci_mpc83xxmitx_config_table,
 116 #endif
 117          },
 118         {
 119 #ifndef CONFIG_PCI_PNP
 120               config_table:pci_mpc83xxmitx_config_table,
 121 #endif
 122          }
 123 };
 124 #endif                          /* CONFIG_PCI */
 125
 126 int dram_init(void)
 127 {
 128         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 129         u32 msize = 0;
 130 #ifdef CONFIG_DDR_ECC
 131         volatile ddr83xx_t *ddr = &im->ddr;
 132 #endif
 133
 134         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 135                 return -ENXIO;
 136
 137         /* DDR SDRAM - Main SODIMM */
 138         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 139 #ifdef CONFIG_SPD_EEPROM
 140         msize = spd_sdram();
 141 #else
 142         msize = fixed_sdram();
 143 #endif
 144
 145 #ifdef CONFIG_DDR_ECC
 146         if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
 147                 /* Unlike every other board, on the 83xx spd_sdram() returns
 148                    megabytes instead of just bytes.  That's why we need to
 149                    multiple by 1MB when calling ddr_enable_ecc(). */
 150                 ddr_enable_ecc(msize * 1048576);
 151 #endif
 152
 153         /* return total bus RAM size(bytes) */
 154         gd->ram_size = msize * 1024 * 1024;
 155
 156         return 0;
 157 }
 158
 159 int checkboard(void)
 160 {
 161 #ifdef CONFIG_TARGET_MPC8349ITX
 162         puts("Board: Freescale MPC8349E-mITX\n");
 163 #else
 164         puts("Board: Freescale MPC8349E-mITX-GP\n");
 165 #endif
 166
 167         return 0;
 168 }
 169
 170 /*
 171  * Implement a work-around for a hardware problem with compact
 172  * flash.
 173  *
 174  * Program the UPM if compact flash is enabled.
 175  */
 176 int misc_init_f(void)
 177 {
 178 #ifdef CONFIG_VSC7385_ENET
 179         volatile u32 *vsc7385_cpuctrl;
 180
 181         /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
 182            default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
 183            means it is 0 when the IRQ is not active.  This makes the wire-AND
 184            logic always assert IRQ7 to CPU even if there is no request from the
 185            switch.  Since the compact flash and the switch share the same IRQ,
 186            the Linux kernel will think that the compact flash is requesting irq
 187            and get stuck when it tries to clear the IRQ.  Thus we need to set
 188            the L2_IRQ0 and L2_IRQ1 to active low.
 189
 190            The following code sets the L1_IRQ and L2_IRQ polarity to active low.
 191            Without this code, compact flash will not work in Linux because
 192            unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
 193            don't enable compact flash for U-Boot.
 194          */
 195
 196         vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
 197         *vsc7385_cpuctrl |= 0x0c;
 198 #endif
 199
 200 #ifdef CONFIG_COMPACT_FLASH
 201         /* UPM Table Configuration Code */
 202         static uint UPMATable[] = {
 203                 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
 204                 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
 205                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 206                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 207                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
 208                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 209                 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
 210                 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
 211                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 212                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 213                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 214                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 215                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 216                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 217                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 218                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 219         };
 220         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 221
 222         set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 223         set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 224
 225         /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
 226            GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
 227          */
 228         immap->im_lbc.mamr = 0x08404440;
 229
 230         upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
 231
 232         puts("UPMA:  Configured for compact flash\n");
 233 #endif
 234
 235         return 0;
 236 }
 237
 238 /*
 239  * Miscellaneous late-boot configurations
 240  *
 241  * Make sure the EEPROM has the HRCW correctly programmed.
 242  * Make sure the RTC is correctly programmed.
 243  *
 244  * The MPC8349E-mITX can be configured to load the HRCW from
 245  * EEPROM instead of flash.  This is controlled via jumpers
 246  * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
 247  * jumpered), but if they're set to 001 or 010, then the HRCW is
 248  * read from the "I2C EEPROM".
 249  *
 250  * This function makes sure that the I2C EEPROM is programmed
 251  * correctly.
 252  *
 253  * If a VSC7385 microcode image is present, then upload it.
 254  */
 255 int misc_init_r(void)
 256 {
 257         int rc = 0;
 258
 259 #if defined(CONFIG_SYS_I2C)
 260         unsigned int orig_bus = i2c_get_bus_num();
 261         u8 i2c_data;
 262
 263 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 264         u8 ds1339_data[17];
 265 #endif
 266
 267 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 268         static u8 eeprom_data[] =       /* HRCW data */
 269         {
 270                 0xAA, 0x55, 0xAA,       /* Preamble */
 271                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 272                 0x02, 0x40,             /* RCWL ADDR=0x0_0900 */
 273                 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
 274                 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
 275                 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
 276                 CONFIG_SYS_HRCW_LOW & 0xFF,
 277                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 278                 0x02, 0x41,             /* RCWH ADDR=0x0_0904 */
 279                 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
 280                 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
 281                 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
 282                 CONFIG_SYS_HRCW_HIGH & 0xFF
 283         };
 284
 285         u8 data[sizeof(eeprom_data)];
 286 #endif
 287
 288         printf("Board revision: ");
 289         i2c_set_bus_num(1);
 290         if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 291                 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 292         else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 293                 printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 294         else {
 295                 printf("Unknown\n");
 296                 rc = 1;
 297         }
 298
 299 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 300         i2c_set_bus_num(0);
 301
 302         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
 303                 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
 304                         if (i2c_write
 305                             (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
 306                              sizeof(eeprom_data)) != 0) {
 307                                 puts("Failure writing the HRCW to EEPROM via I2C.\n");
 308                                 rc = 1;
 309                         }
 310                 }
 311         } else {
 312                 puts("Failure reading the HRCW from EEPROM via I2C.\n");
 313                 rc = 1;
 314         }
 315 #endif
 316
 317 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 318         i2c_set_bus_num(1);
 319
 320         if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
 321             == 0) {
 322
 323                 /* Work-around for MPC8349E-mITX bug #13601.
 324                    If the RTC does not contain valid register values, the DS1339
 325                    Linux driver will not work.
 326                  */
 327
 328                 /* Make sure status register bits 6-2 are zero */
 329                 ds1339_data[0x0f] &= ~0x7c;
 330
 331                 /* Check for a valid day register value */
 332                 ds1339_data[0x03] &= ~0xf8;
 333                 if (ds1339_data[0x03] == 0) {
 334                         ds1339_data[0x03] = 1;
 335                 }
 336
 337                 /* Check for a valid date register value */
 338                 ds1339_data[0x04] &= ~0xc0;
 339                 if ((ds1339_data[0x04] == 0) ||
 340                     ((ds1339_data[0x04] & 0x0f) > 9) ||
 341                     (ds1339_data[0x04] >= 0x32)) {
 342                         ds1339_data[0x04] = 1;
 343                 }
 344
 345                 /* Check for a valid month register value */
 346                 ds1339_data[0x05] &= ~0x60;
 347
 348                 if ((ds1339_data[0x05] == 0) ||
 349                     ((ds1339_data[0x05] & 0x0f) > 9) ||
 350                     ((ds1339_data[0x05] >= 0x13)
 351                      && (ds1339_data[0x05] <= 0x19))) {
 352                         ds1339_data[0x05] = 1;
 353                 }
 354
 355                 /* Enable Oscillator and rate select */
 356                 ds1339_data[0x0e] = 0x1c;
 357
 358                 /* Work-around for MPC8349E-mITX bug #13330.
 359                    Ensure that the RTC control register contains the value 0x1c.
 360                    This affects SATA performance.
 361                  */
 362
 363                 if (i2c_write
 364                     (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
 365                      sizeof(ds1339_data))) {
 366                         puts("Failure writing to the RTC via I2C.\n");
 367                         rc = 1;
 368                 }
 369         } else {
 370                 puts("Failure reading from the RTC via I2C.\n");
 371                 rc = 1;
 372         }
 373 #endif
 374
 375         i2c_set_bus_num(orig_bus);
 376 #endif
 377
 378 #ifdef CONFIG_VSC7385_IMAGE
 379         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 380                 CONFIG_VSC7385_IMAGE_SIZE)) {
 381                 puts("Failure uploading VSC7385 microcode.\n");
 382                 rc = 1;
 383         }
 384 #endif
 385
 386         return rc;
 387 }
 388
 389 #if defined(CONFIG_OF_BOARD_SETUP)
 390 int ft_board_setup(void *blob, bd_t *bd)
 391 {
 392         ft_cpu_setup(blob, bd);
 393 #ifdef CONFIG_PCI
 394         ft_pci_setup(blob, bd);
 395 #endif
 396
 397         return 0;
 398 }
 399 #endif