board/freescale/mpc8349itx/mpc8349itx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  */
   5
   6 #include <common.h>
   7 #include <fdt_support.h>
   8 #include <init.h>
   9 #include <ioports.h>
  10 #include <log.h>
  11 #include <mpc83xx.h>
  12 #include <i2c.h>
  13 #include <miiphy.h>
  14 #include <vsc7385.h>
  15 #ifdef CONFIG_PCI
  16 #include <asm/mpc8349_pci.h>
  17 #include <pci.h>
  18 #endif
  19 #include <spd_sdram.h>
  20 #include <asm/mmu.h>
  21 #if defined(CONFIG_OF_LIBFDT)
  22 #include <linux/libfdt.h>
  23 #endif
  24 #include <linux/delay.h>
  25
  26 #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
  27 #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #ifndef CONFIG_SPD_EEPROM
  32 /*************************************************************************
  33  *  fixed sdram init -- doesn't use serial presence detect.
  34  ************************************************************************/
  35 int fixed_sdram(void)
  36 {
  37         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  38         /* The size of RAM, in bytes */
  39         u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
  40         u32 ddr_size_log2 = __ilog2(ddr_size);
  41
  42         im->sysconf.ddrlaw[0].ar =
  43             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  44         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  45
  46 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  47 #warning Chip select bounds is only configurable in 16MB increments
  48 #endif
  49         im->ddr.csbnds[0].csbnds =
  50                 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  51                 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  52                                 CSBNDS_EA_SHIFT) & CSBNDS_EA);
  53         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  54
  55         /* Only one CS for DDR */
  56         im->ddr.cs_config[1] = 0;
  57         im->ddr.cs_config[2] = 0;
  58         im->ddr.cs_config[3] = 0;
  59
  60         debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
  61         debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
  62
  63         debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
  64         debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
  65
  66         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  67         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
  68         im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
  69         im->ddr.sdram_mode =
  70             (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
  71         im->ddr.sdram_interval =
  72             (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
  73                                                        SDRAM_INTERVAL_BSTOPRE_SHIFT);
  74         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  75
  76         udelay(200);
  77
  78         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  79
  80         debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
  81         debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
  82         debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
  83         debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
  84         debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
  85
  86         return CONFIG_SYS_DDR_SIZE;
  87 }
  88 #endif
  89
  90 #ifdef CONFIG_PCI
  91 /*
  92  * Initialize PCI Devices, report devices found
  93  */
  94 #ifndef CONFIG_PCI_PNP
  95 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
  96         {
  97          PCI_ANY_ID,
  98          PCI_ANY_ID,
  99          PCI_ANY_ID,
 100          PCI_ANY_ID,
 101          0x0f,
 102          PCI_ANY_ID,
 103          pci_cfgfunc_config_device,
 104          {
 105           PCI_ENET0_IOADDR,
 106           PCI_ENET0_MEMADDR,
 107           PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
 108          },
 109         {}
 110 }
 111 #endif
 112
 113 volatile static struct pci_controller hose[] = {
 114         {
 115 #ifndef CONFIG_PCI_PNP
 116               config_table:pci_mpc83xxmitx_config_table,
 117 #endif
 118          },
 119         {
 120 #ifndef CONFIG_PCI_PNP
 121               config_table:pci_mpc83xxmitx_config_table,
 122 #endif
 123          }
 124 };
 125 #endif                          /* CONFIG_PCI */
 126
 127 int dram_init(void)
 128 {
 129         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 130         u32 msize = 0;
 131 #ifdef CONFIG_DDR_ECC
 132         volatile ddr83xx_t *ddr = &im->ddr;
 133 #endif
 134
 135         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 136                 return -ENXIO;
 137
 138         /* DDR SDRAM - Main SODIMM */
 139         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 140 #ifdef CONFIG_SPD_EEPROM
 141         msize = spd_sdram();
 142 #else
 143         msize = fixed_sdram();
 144 #endif
 145
 146 #ifdef CONFIG_DDR_ECC
 147         if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
 148                 /* Unlike every other board, on the 83xx spd_sdram() returns
 149                    megabytes instead of just bytes.  That's why we need to
 150                    multiple by 1MB when calling ddr_enable_ecc(). */
 151                 ddr_enable_ecc(msize * 1048576);
 152 #endif
 153
 154         /* return total bus RAM size(bytes) */
 155         gd->ram_size = msize * 1024 * 1024;
 156
 157         return 0;
 158 }
 159
 160 int checkboard(void)
 161 {
 162 #ifdef CONFIG_TARGET_MPC8349ITX
 163         puts("Board: Freescale MPC8349E-mITX\n");
 164 #else
 165         puts("Board: Freescale MPC8349E-mITX-GP\n");
 166 #endif
 167
 168         return 0;
 169 }
 170
 171 /*
 172  * Implement a work-around for a hardware problem with compact
 173  * flash.
 174  *
 175  * Program the UPM if compact flash is enabled.
 176  */
 177 int misc_init_f(void)
 178 {
 179 #ifdef CONFIG_VSC7385_ENET
 180         volatile u32 *vsc7385_cpuctrl;
 181
 182         /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
 183            default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
 184            means it is 0 when the IRQ is not active.  This makes the wire-AND
 185            logic always assert IRQ7 to CPU even if there is no request from the
 186            switch.  Since the compact flash and the switch share the same IRQ,
 187            the Linux kernel will think that the compact flash is requesting irq
 188            and get stuck when it tries to clear the IRQ.  Thus we need to set
 189            the L2_IRQ0 and L2_IRQ1 to active low.
 190
 191            The following code sets the L1_IRQ and L2_IRQ polarity to active low.
 192            Without this code, compact flash will not work in Linux because
 193            unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
 194            don't enable compact flash for U-Boot.
 195          */
 196
 197         vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
 198         *vsc7385_cpuctrl |= 0x0c;
 199 #endif
 200
 201 #ifdef CONFIG_COMPACT_FLASH
 202         /* UPM Table Configuration Code */
 203         static uint UPMATable[] = {
 204                 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
 205                 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
 206                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 207                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 208                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
 209                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 210                 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
 211                 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
 212                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 213                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 214                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 215                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 216                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 217                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 218                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 219                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 220         };
 221         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 222
 223         set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 224         set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 225
 226         /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
 227            GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
 228          */
 229         immap->im_lbc.mamr = 0x08404440;
 230
 231         upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
 232
 233         puts("UPMA:  Configured for compact flash\n");
 234 #endif
 235
 236         return 0;
 237 }
 238
 239 /*
 240  * Miscellaneous late-boot configurations
 241  *
 242  * Make sure the EEPROM has the HRCW correctly programmed.
 243  * Make sure the RTC is correctly programmed.
 244  *
 245  * The MPC8349E-mITX can be configured to load the HRCW from
 246  * EEPROM instead of flash.  This is controlled via jumpers
 247  * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
 248  * jumpered), but if they're set to 001 or 010, then the HRCW is
 249  * read from the "I2C EEPROM".
 250  *
 251  * This function makes sure that the I2C EEPROM is programmed
 252  * correctly.
 253  *
 254  * If a VSC7385 microcode image is present, then upload it.
 255  */
 256 int misc_init_r(void)
 257 {
 258         int rc = 0;
 259
 260 #if defined(CONFIG_SYS_I2C)
 261         unsigned int orig_bus = i2c_get_bus_num();
 262         u8 i2c_data;
 263
 264 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 265         u8 ds1339_data[17];
 266 #endif
 267
 268 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 269         static u8 eeprom_data[] =       /* HRCW data */
 270         {
 271                 0xAA, 0x55, 0xAA,       /* Preamble */
 272                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 273                 0x02, 0x40,             /* RCWL ADDR=0x0_0900 */
 274                 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
 275                 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
 276                 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
 277                 CONFIG_SYS_HRCW_LOW & 0xFF,
 278                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 279                 0x02, 0x41,             /* RCWH ADDR=0x0_0904 */
 280                 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
 281                 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
 282                 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
 283                 CONFIG_SYS_HRCW_HIGH & 0xFF
 284         };
 285
 286         u8 data[sizeof(eeprom_data)];
 287 #endif
 288
 289         printf("Board revision: ");
 290         i2c_set_bus_num(1);
 291         if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 292                 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 293         else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 294                 printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 295         else {
 296                 printf("Unknown\n");
 297                 rc = 1;
 298         }
 299
 300 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 301         i2c_set_bus_num(0);
 302
 303         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
 304                 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
 305                         if (i2c_write
 306                             (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
 307                              sizeof(eeprom_data)) != 0) {
 308                                 puts("Failure writing the HRCW to EEPROM via I2C.\n");
 309                                 rc = 1;
 310                         }
 311                 }
 312         } else {
 313                 puts("Failure reading the HRCW from EEPROM via I2C.\n");
 314                 rc = 1;
 315         }
 316 #endif
 317
 318 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 319         i2c_set_bus_num(1);
 320
 321         if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
 322             == 0) {
 323
 324                 /* Work-around for MPC8349E-mITX bug #13601.
 325                    If the RTC does not contain valid register values, the DS1339
 326                    Linux driver will not work.
 327                  */
 328
 329                 /* Make sure status register bits 6-2 are zero */
 330                 ds1339_data[0x0f] &= ~0x7c;
 331
 332                 /* Check for a valid day register value */
 333                 ds1339_data[0x03] &= ~0xf8;
 334                 if (ds1339_data[0x03] == 0) {
 335                         ds1339_data[0x03] = 1;
 336                 }
 337
 338                 /* Check for a valid date register value */
 339                 ds1339_data[0x04] &= ~0xc0;
 340                 if ((ds1339_data[0x04] == 0) ||
 341                     ((ds1339_data[0x04] & 0x0f) > 9) ||
 342                     (ds1339_data[0x04] >= 0x32)) {
 343                         ds1339_data[0x04] = 1;
 344                 }
 345
 346                 /* Check for a valid month register value */
 347                 ds1339_data[0x05] &= ~0x60;
 348
 349                 if ((ds1339_data[0x05] == 0) ||
 350                     ((ds1339_data[0x05] & 0x0f) > 9) ||
 351                     ((ds1339_data[0x05] >= 0x13)
 352                      && (ds1339_data[0x05] <= 0x19))) {
 353                         ds1339_data[0x05] = 1;
 354                 }
 355
 356                 /* Enable Oscillator and rate select */
 357                 ds1339_data[0x0e] = 0x1c;
 358
 359                 /* Work-around for MPC8349E-mITX bug #13330.
 360                    Ensure that the RTC control register contains the value 0x1c.
 361                    This affects SATA performance.
 362                  */
 363
 364                 if (i2c_write
 365                     (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
 366                      sizeof(ds1339_data))) {
 367                         puts("Failure writing to the RTC via I2C.\n");
 368                         rc = 1;
 369                 }
 370         } else {
 371                 puts("Failure reading from the RTC via I2C.\n");
 372                 rc = 1;
 373         }
 374 #endif
 375
 376         i2c_set_bus_num(orig_bus);
 377 #endif
 378
 379 #ifdef CONFIG_VSC7385_IMAGE
 380         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 381                 CONFIG_VSC7385_IMAGE_SIZE)) {
 382                 puts("Failure uploading VSC7385 microcode.\n");
 383                 rc = 1;
 384         }
 385 #endif
 386
 387         return rc;
 388 }
 389
 390 #if defined(CONFIG_OF_BOARD_SETUP)
 391 int ft_board_setup(void *blob, bd_t *bd)
 392 {
 393         ft_cpu_setup(blob, bd);
 394 #ifdef CONFIG_PCI
 395         ft_pci_setup(blob, bd);
 396 #endif
 397
 398         return 0;
 399 }
 400 #endif