board/freescale/mpc8349emds/pci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <init.h>
   7 #include <asm/mmu.h>
   8 #include <asm/io.h>
   9 #include <common.h>
  10 #include <mpc83xx.h>
  11 #include <pci.h>
  12 #include <i2c.h>
  13 #include <asm/fsl_i2c.h>
  14 #include <linux/delay.h>
  15
  16 static struct pci_region pci1_regions[] = {
  17         {
  18                 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  19                 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  20                 size: CONFIG_SYS_PCI1_MEM_SIZE,
  21                 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  22         },
  23         {
  24                 bus_start: CONFIG_SYS_PCI1_IO_BASE,
  25                 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  26                 size: CONFIG_SYS_PCI1_IO_SIZE,
  27                 flags: PCI_REGION_IO
  28         },
  29         {
  30                 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  31                 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  32                 size: CONFIG_SYS_PCI1_MMIO_SIZE,
  33                 flags: PCI_REGION_MEM
  34         },
  35 };
  36
  37 #ifdef CONFIG_MPC83XX_PCI2
  38 static struct pci_region pci2_regions[] = {
  39         {
  40                 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
  41                 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
  42                 size: CONFIG_SYS_PCI2_MEM_SIZE,
  43                 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  44         },
  45         {
  46                 bus_start: CONFIG_SYS_PCI2_IO_BASE,
  47                 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
  48                 size: CONFIG_SYS_PCI2_IO_SIZE,
  49                 flags: PCI_REGION_IO
  50         },
  51         {
  52                 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
  53                 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
  54                 size: CONFIG_SYS_PCI2_MMIO_SIZE,
  55                 flags: PCI_REGION_MEM
  56         },
  57 };
  58 #endif
  59
  60 #ifndef CONFIG_PCISLAVE
  61 void pib_init(void)
  62 {
  63         u8 val8, orig_i2c_bus;
  64         /*
  65          * Assign PIB PMC slot to desired PCI bus
  66          */
  67         /* Switch temporarily to I2C bus #2 */
  68         orig_i2c_bus = i2c_get_bus_num();
  69         i2c_set_bus_num(1);
  70
  71         val8 = 0;
  72         i2c_write(0x23, 0x6, 1, &val8, 1);
  73         i2c_write(0x23, 0x7, 1, &val8, 1);
  74         val8 = 0xff;
  75         i2c_write(0x23, 0x2, 1, &val8, 1);
  76         i2c_write(0x23, 0x3, 1, &val8, 1);
  77
  78         val8 = 0;
  79         i2c_write(0x26, 0x6, 1, &val8, 1);
  80         val8 = 0x34;
  81         i2c_write(0x26, 0x7, 1, &val8, 1);
  82 #if defined(CONFIG_PCI_64BIT)
  83         val8 = 0xf4;    /* PMC2:PCI1/64-bit */
  84 #elif defined(CONFIG_PCI_ALL_PCI1)
  85         val8 = 0xf3;    /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
  86 #elif defined(CONFIG_PCI_ONE_PCI1)
  87         val8 = 0xf9;    /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
  88 #else
  89         val8 = 0xf5;    /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
  90 #endif
  91         i2c_write(0x26, 0x2, 1, &val8, 1);
  92         val8 = 0xff;
  93         i2c_write(0x26, 0x3, 1, &val8, 1);
  94         val8 = 0;
  95         i2c_write(0x27, 0x6, 1, &val8, 1);
  96         i2c_write(0x27, 0x7, 1, &val8, 1);
  97         val8 = 0xff;
  98         i2c_write(0x27, 0x2, 1, &val8, 1);
  99         val8 = 0xef;
 100         i2c_write(0x27, 0x3, 1, &val8, 1);
 101         asm("eieio");
 102
 103 #if defined(CONFIG_PCI_64BIT)
 104         printf("PCI1: 64-bit on PMC2\n");
 105 #elif defined(CONFIG_PCI_ALL_PCI1)
 106         printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
 107 #elif defined(CONFIG_PCI_ONE_PCI1)
 108         printf("PCI1: 32-bit on PMC1\n");
 109         printf("PCI2: 32-bit on PMC2, PMC3\n");
 110 #else
 111         printf("PCI1: 32-bit on PMC1, PMC2\n");
 112         printf("PCI2: 32-bit on PMC3\n");
 113 #endif
 114         /* Reset to original I2C bus */
 115         i2c_set_bus_num(orig_i2c_bus);
 116 }
 117
 118 void pci_init_board(void)
 119 {
 120         volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 121         volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 122         volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 123 #ifndef CONFIG_MPC83XX_PCI2
 124         struct pci_region *reg[] = { pci1_regions };
 125 #else
 126         struct pci_region *reg[] = { pci1_regions, pci2_regions };
 127 #endif
 128
 129         /* initialize the PCA9555PW IO expander on the PIB board */
 130         pib_init();
 131
 132         /* Enable all 8 PCI_CLK_OUTPUTS */
 133         clk->occr = 0xff000000;
 134         udelay(2000);
 135
 136         /* Configure PCI Local Access Windows */
 137         pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 138         pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 139
 140         pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 141         pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 142
 143         udelay(2000);
 144
 145 #ifndef CONFIG_MPC83XX_PCI2
 146         mpc83xx_pci_init(1, reg);
 147 #else
 148         mpc83xx_pci_init(2, reg);
 149 #endif
 150 }
 151
 152 #else
 153 void pci_init_board(void)
 154 {
 155         volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 156         volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 157         volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
 158         struct pci_region *reg[] = { pci1_regions };
 159
 160         /* Configure PCI Local Access Windows */
 161         pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 162         pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 163
 164         pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 165         pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 166
 167         mpc83xx_pci_init(1, reg);
 168
 169         /* Configure PCI Inbound Translation Windows (3 1MB windows) */
 170         pci_ctrl->pitar0 = 0x0;
 171         pci_ctrl->pibar0 = 0x0;
 172         pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
 173                            PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
 174
 175         pci_ctrl->pitar1  = 0x0;
 176         pci_ctrl->pibar1  = 0x0;
 177         pci_ctrl->piebar1 = 0x0;
 178         pci_ctrl->piwar1  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
 179                             PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
 180
 181         pci_ctrl->pitar2  = 0x0;
 182         pci_ctrl->pibar2  = 0x0;
 183         pci_ctrl->piebar2 = 0x0;
 184         pci_ctrl->piwar2  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
 185                             PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
 186
 187         /* Unlock the configuration bit */
 188         mpc83xx_pcislave_unlock(0);
 189         printf("PCI:   Agent mode enabled\n");
 190 }
 191 #endif /* CONFIG_PCISLAVE */