1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
5 * Authors: Nick.Spence@freescale.com
6 * Wilson.Lo@freescale.com
7 * scottwood@freescale.com
13 #include <spd_sdram.h>
14 #include <linux/delay.h>
16 #include <asm/bitops.h>
19 #include <asm/processor.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
24 static void resume_from_sleep(void)
26 u32 magic = *(u32 *)0;
28 typedef void (*func_t)(void);
29 func_t resume = *(func_t *)4;
31 if (magic == 0xf5153ae5)
34 gd->flags &= ~GD_FLG_SILENT;
35 puts("\nResume from sleep failed: bad magic word\n");
39 /* Fixed sdram init -- doesn't use serial presence detect.
41 * This is useful for faster booting in configs where the RAM is unlikely
42 * to be changed, or for things like NAND booting where space is tight.
44 static long fixed_sdram(void)
46 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
48 #ifndef CONFIG_SYS_RAMBOOT
49 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
50 u32 msize_log2 = __ilog2(msize);
52 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
53 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
54 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
57 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
58 * or the DDR2 controller may fail to initialize correctly.
62 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
63 #warning Chip select bounds is only configurable in 16MB increments
65 im->ddr.csbnds[0].csbnds =
66 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
67 (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
69 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
71 /* Currently we use only one CS, so disable the other bank. */
72 im->ddr.cs_config[1] = 0;
74 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
75 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
76 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
77 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
78 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
80 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
81 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
82 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
85 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
87 im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
88 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
89 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
91 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
94 /* enable DDR controller */
95 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
103 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
104 volatile fsl_lbc_t *lbc = &im->im_lbc;
107 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
110 /* DDR SDRAM - Main SODIMM */
111 msize = fixed_sdram();
113 /* Local Bus setup lbcr and mrtpr */
114 lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
115 /* LB refresh timer prescal, 266MHz/32 */
116 lbc->mrtpr = 0x20000000;
119 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
120 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
124 /* return total bus SDRAM size(bytes) -- DDR */
125 gd->ram_size = msize;