board/freescale/m54455evb/m54455evb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2000-2003
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
   7  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8  */
   9
  10 #include <common.h>
  11 #include <init.h>
  12 #include <pci.h>
  13 #include <asm/immap.h>
  14 #include <asm/io.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 int checkboard(void)
  19 {
  20         puts("Board: ");
  21         puts("Freescale M54455 EVB\n");
  22         return 0;
  23 };
  24
  25 int dram_init(void)
  26 {
  27         u32 dramsize;
  28 #ifdef CONFIG_CF_SBF
  29         /*
  30          * Serial Boot: The dram is already initialized in start.S
  31          * only require to return DRAM size
  32          */
  33         dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
  34 #else
  35         sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
  36         gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
  37         u32 i;
  38
  39         dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
  40
  41         for (i = 0x13; i < 0x20; i++) {
  42                 if (dramsize == (1 << i))
  43                         break;
  44         }
  45         i--;
  46
  47         out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
  48
  49         out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
  50         out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
  51
  52         out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
  53         out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
  54
  55         /* Issue PALL */
  56         out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
  57
  58         /* Issue LEMR */
  59         out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
  60         out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
  61
  62         udelay(500);
  63
  64         /* Issue PALL */
  65         out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
  66
  67         /* Perform two refresh cycles */
  68         out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
  69         out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
  70
  71         out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
  72
  73         out_be32(&sdram->sdcr,
  74                 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
  75
  76         udelay(100);
  77 #endif
  78         gd->ram_size = dramsize << 1;
  79
  80         return 0;
  81 };
  82
  83 int testdram(void)
  84 {
  85         /* TODO: XXX XXX XXX */
  86         printf("DRAM test not implemented!\n");
  87
  88         return (0);
  89 }
  90
  91 #if defined(CONFIG_IDE)
  92 #include <ata.h>
  93
  94 int ide_preinit(void)
  95 {
  96         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  97         u32 tmp;
  98
  99         tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
 100         setbits_8(&gpio->par_fec, tmp);
 101         tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
 102                 (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
 103         setbits_be16(&gpio->par_feci2c, tmp);
 104
 105         setbits_be16(&gpio->par_ata,
 106                 GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
 107                 GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
 108                 GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
 109                 GPIO_PAR_ATA_IORDY_IORDY);
 110         setbits_be16(&gpio->par_pci,
 111                 GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
 112
 113         return (0);
 114 }
 115
 116 void ide_set_reset(int idereset)
 117 {
 118         atac_t *ata = (atac_t *) MMAP_ATA;
 119         long period;
 120         /*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 121         int piotms[5][9] = {
 122                 {70, 165, 60, 30, 50, 5, 20, 0, 35},    /* PIO 0 */
 123                 {50, 125, 45, 20, 35, 5, 15, 0, 35},    /* PIO 1 */
 124                 {30, 100, 30, 15, 20, 5, 10, 0, 35},    /* PIO 2 */
 125                 {30, 80, 30, 10, 20, 5, 10, 0, 35},     /* PIO 3 */
 126                 {25, 70, 20, 10, 20, 5, 10, 0, 35}
 127         };                      /* PIO 4 */
 128
 129         if (idereset) {
 130                 /* control reset */
 131                 out_8(&ata->cr, 0);
 132                 udelay(10000);
 133         } else {
 134 #define CALC_TIMING(t) (t + period - 1) / period
 135                 period = 1000000000 / gd->bus_clk;      /* period in ns */
 136
 137                 /*ata->ton = CALC_TIMING (180); */
 138                 out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
 139                 out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
 140                 out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
 141                 out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
 142                 out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
 143                 out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
 144                 out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
 145
 146                 /* IORDY enable */
 147                 out_8(&ata->cr, 0x40);
 148                 udelay(200000);
 149                 /* IORDY enable */
 150                 setbits_8(&ata->cr, 0x01);
 151         }
 152 }
 153 #endif
 154
 155 #if defined(CONFIG_PCI)
 156 /*
 157  * Initialize PCI devices, report devices found.
 158  */
 159 static struct pci_controller hose;
 160 extern void pci_mcf5445x_init(struct pci_controller *hose);
 161
 162 void pci_init_board(void)
 163 {
 164         pci_mcf5445x_init(&hose);
 165 }
 166 #endif                          /* CONFIG_PCI */
 167
 168 #if defined(CONFIG_FLASH_CFI_LEGACY)
 169 #include <flash.h>
 170 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
 171 {
 172         int sect[] = CONFIG_SYS_ATMEL_SECT;
 173         int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
 174         int i, j, k;
 175
 176         if (base != CONFIG_SYS_ATMEL_BASE)
 177                 return 0;
 178
 179         info->flash_id          = 0x01000000;
 180         info->portwidth         = 1;
 181         info->chipwidth         = 1;
 182         info->buffer_size       = 1;
 183         info->erase_blk_tout    = 16384;
 184         info->write_tout        = 2;
 185         info->buffer_write_tout = 5;
 186         info->vendor            = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
 187         info->cmd_reset         = 0x00F0;
 188         info->interface         = FLASH_CFI_X8;
 189         info->legacy_unlock     = 0;
 190         info->manufacturer_id   = (u16) ATM_MANUFACT;
 191         info->device_id         = ATM_ID_LV040;
 192         info->device_id2        = 0;
 193
 194         info->ext_addr          = 0;
 195         info->cfi_version       = 0x3133;
 196         info->cfi_offset        = 0x0000;
 197         info->addr_unlock1      = 0x00000555;
 198         info->addr_unlock2      = 0x000002AA;
 199         info->name              = "CFI conformant";
 200
 201         info->size              = 0;
 202         info->sector_count      = CONFIG_SYS_ATMEL_TOTALSECT;
 203         info->start[0] = base;
 204         for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
 205                 info->size += sect[i] * sectsz[i];
 206
 207                 for (j = 0; j < sect[i]; j++, k++) {
 208                         info->start[k + 1] = info->start[k] + sectsz[i];
 209                         info->protect[k] = 0;
 210                 }
 211         }
 212
 213         return 1;
 214 }
 215 #endif                          /* CONFIG_SYS_FLASH_CFI */