2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/m5329.h>
30 #include <asm/immap_5329.h>
35 DECLARE_GLOBAL_DATA_PTR;
40 puts("Freescale FireEngine 5329 EVB\n");
44 long int initdram(int board_type)
46 volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
49 dramsize = CFG_SDRAM_SIZE * 0x100000;
51 for (i = 0x13; i < 0x20; i++) {
52 if (dramsize == (1 << i))
57 sdram->cs0 = (CFG_SDRAM_BASE | i);
58 sdram->cfg1 = CFG_SDRAM_CFG1;
59 sdram->cfg2 = CFG_SDRAM_CFG2;
62 sdram->ctrl = CFG_SDRAM_CTRL | 2;
65 sdram->mode = CFG_SDRAM_EMOD;
66 sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
71 sdram->ctrl = (CFG_SDRAM_CTRL | 2);
73 /* Perform two refresh cycles */
74 sdram->ctrl = CFG_SDRAM_CTRL | 4;
75 sdram->ctrl = CFG_SDRAM_CTRL | 4;
77 sdram->mode = CFG_SDRAM_MODE;
79 sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
88 /* TODO: XXX XXX XXX */
89 printf("DRAM test not implemented!\n");
97 /* This sync function is PowerPC intruction,
98 coldfire does not have this instruction. Dummy function */
102 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
106 int fecpin_setclear(struct eth_device *dev, int setclear)
108 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
111 gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
113 GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
115 gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
117 ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
122 #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
125 /* Make MII read/write commands for the FEC. */
126 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
129 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
130 (REG & 0x1f) << 18) | \
133 /* PHY identification */
134 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
135 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
136 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
137 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
138 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
139 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
140 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
141 #define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
142 #define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
144 #define STR_ID_LXT970 "LXT970"
145 #define STR_ID_LXT971 "LXT971"
146 #define STR_ID_82555 "Intel82555"
147 #define STR_ID_QS6612 "QS6612"
148 #define STR_ID_AMD79C784 "AMD79C784"
149 #define STR_ID_LSI80225 "LSI80225"
150 #define STR_ID_LSI80225B "LSI80225/B"
151 #define STR_ID_DP83848VV "N83848"
152 #define STR_ID_DP83849 "N83849"
154 /****************************************************************************
155 * mii_init -- Initialize the MII for MII command without ethernet
156 * This function is a subset of eth_init
157 ****************************************************************************
159 void mii_reset(struct fec_info_s *info)
161 volatile fec_t *fecp = (fec_t *) (info->miibase);
164 fecp->ecr = FEC_ECR_RESET;
165 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
168 if (i == FEC_RESET_DELAY) {
169 printf("FEC_RESET_DELAY timeout\n");
173 /* send command to phy using mii, wait for result */
174 uint mii_send(uint mii_cmd)
176 struct fec_info_s *info;
177 struct eth_device *dev;
182 /* retrieve from register structure */
186 ep = (fec_t *) info->miibase;
188 ep->mmfr = mii_cmd; /* command to phy */
190 /* wait for mii complete */
191 while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
195 if (j >= MCFFEC_TOUT_LOOP) {
196 printf("MII not complete\n");
200 mii_reply = ep->mmfr; /* result from phy */
201 ep->eir = FEC_EIR_MII; /* clear MII complete */
203 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
204 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
207 return (mii_reply & 0xffff); /* data read from phy */
209 #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
211 #if defined(CFG_DISCOVER_PHY)
212 int mii_discover_phy(struct eth_device *dev)
214 #define MAX_PHY_PASSES 11
215 struct fec_info_s *info = dev->priv;
219 if (info->phyname_init)
220 return info->phy_addr;
222 phyaddr = -1; /* didn't find a PHY yet */
223 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
225 /* PHY may need more time to recover from reset.
226 * The LXT970 needs 50ms typical, no maximum is
227 * specified, so wait 10ms before try again.
228 * With 11 passes this gives it 100ms to wake up.
230 udelay(10000); /* wait 10ms */
233 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
235 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
237 printf("PHY type 0x%x pass %d type\n", phytype, pass);
239 if (phytype != 0xffff) {
243 mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
245 switch (phytype & 0xffffffff) {
246 case PHY_ID_DP83848VV:
247 strcpy(info->phy_name,
249 info->phyname_init = 1;
252 strcpy(info->phy_name, "unknown");
253 info->phyname_init = 1;
258 printf("PHY @ 0x%x pass %d type ", phyno, pass);
259 switch (phytype & 0xffffffff) {
260 case PHY_ID_DP83848VV:
261 printf(STR_ID_DP83848VV);
264 printf("0x%08x\n", phytype);
272 printf("No PHY device found.\n");
276 #endif /* CFG_DISCOVER_PHY */
280 volatile fec_t *fecp;
281 struct fec_info_s *info;
282 struct eth_device *dev;
283 int miispd = 0, i = 0;
286 /* retrieve from register structure */
290 fecp = (fec_t *) info->miibase;
292 fecpin_setclear(dev, 1);
296 /* We use strictly polling mode only */
299 /* Clear any pending interrupt */
300 fecp->eir = 0xffffffff;
303 miispd = (gd->bus_clk / 1000000) / 5;
304 fecp->mscr = miispd << 1;
306 info->phy_addr = mii_discover_phy(dev);
308 #define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
309 while (i < MCFFEC_TOUT_LOOP) {
311 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
314 if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
319 if (i >= MCFFEC_TOUT_LOOP) {
320 printf("Auto Negotiation not complete\n");
323 /* adapt to the half/full speed settings */
324 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
325 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
328 /*****************************************************************************
329 * Read and write a MII PHY register, routines used by MII Utilities
331 * FIXME: These routines are expected to return 0 on success, but mii_send
332 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
333 * no PHY connected...
334 * For now always return 0.
335 * FIXME: These routines only work after calling eth_init() at least once!
336 * Otherwise they hang in mii_send() !!! Sorry!
337 *****************************************************************************/
339 int mcffec_miiphy_read(char *devname, unsigned char addr,
340 unsigned char reg, unsigned short *value)
342 short rdreg; /* register working value */
345 printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
347 rdreg = mii_send(mk_mii_read(addr, reg));
352 printf("0x%04x\n", *value);
358 int mcffec_miiphy_write(char *devname, unsigned char addr,
359 unsigned char reg, unsigned short value)
361 short rdreg; /* register working value */
364 printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
367 rdreg = mii_send(mk_mii_write(addr, reg, value));
370 printf("0x%04x\n", value);
376 #endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */