board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <dm/platform_data/serial_pl01x.h>
  10 #include <i2c.h>
  11 #include <malloc.h>
  12 #include <errno.h>
  13 #include <netdev.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/io.h>
  17 #include <fdt_support.h>
  18 #include <linux/libfdt.h>
  19 #include <fsl-mc/fsl_mc.h>
  20 #include <env_internal.h>
  21 #include <efi_loader.h>
  22 #include <asm/arch/mmu.h>
  23 #include <hwconfig.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/config.h>
  26 #include <asm/arch/fsl_serdes.h>
  27 #include <asm/arch/soc.h>
  28 #include "../common/qixis.h"
  29 #include "../common/vid.h"
  30 #include <fsl_immap.h>
  31 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  32
  33 #ifdef CONFIG_EMC2305
  34 #include "../common/emc2305.h"
  35 #endif
  36
  37 #ifdef CONFIG_TARGET_LX2160AQDS
  38 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  39 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  40 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  41 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  42 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  43 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  44 #define SDHC1_BASE_PMUX_DSPI                    2
  45 #define SDHC2_BASE_PMUX_DSPI                    2
  46 #define IIC5_PMUX_SPI3                          3
  47 #endif /* CONFIG_TARGET_LX2160AQDS */
  48
  49 DECLARE_GLOBAL_DATA_PTR;
  50
  51 static struct pl01x_serial_platdata serial0 = {
  52 #if CONFIG_CONS_INDEX == 0
  53         .base = CONFIG_SYS_SERIAL0,
  54 #elif CONFIG_CONS_INDEX == 1
  55         .base = CONFIG_SYS_SERIAL1,
  56 #else
  57 #error "Unsupported console index value."
  58 #endif
  59         .type = TYPE_PL011,
  60 };
  61
  62 U_BOOT_DEVICE(nxp_serial0) = {
  63         .name = "serial_pl01x",
  64         .platdata = &serial0,
  65 };
  66
  67 static struct pl01x_serial_platdata serial1 = {
  68         .base = CONFIG_SYS_SERIAL1,
  69         .type = TYPE_PL011,
  70 };
  71
  72 U_BOOT_DEVICE(nxp_serial1) = {
  73         .name = "serial_pl01x",
  74         .platdata = &serial1,
  75 };
  76
  77 int select_i2c_ch_pca9547(u8 ch)
  78 {
  79         int ret;
  80
  81 #ifndef CONFIG_DM_I2C
  82         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  83 #else
  84         struct udevice *dev;
  85
  86         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  87         if (!ret)
  88                 ret = dm_i2c_write(dev, 0, &ch, 1);
  89 #endif
  90         if (ret) {
  91                 puts("PCA: failed to select proper channel\n");
  92                 return ret;
  93         }
  94
  95         return 0;
  96 }
  97
  98 static void uart_get_clock(void)
  99 {
 100         serial0.clock = get_serial_clock();
 101         serial1.clock = get_serial_clock();
 102 }
 103
 104 int board_early_init_f(void)
 105 {
 106 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 107         i2c_early_init_f();
 108 #endif
 109         /* get required clock for UART IP */
 110         uart_get_clock();
 111
 112 #ifdef CONFIG_EMC2305
 113         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 114         emc2305_init();
 115         set_fan_speed(I2C_EMC2305_PWM);
 116         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 117 #endif
 118
 119         fsl_lsch3_early_init_f();
 120         return 0;
 121 }
 122
 123 #ifdef CONFIG_OF_BOARD_FIXUP
 124 int board_fix_fdt(void *fdt)
 125 {
 126         char *reg_names, *reg_name;
 127         int names_len, old_name_len, new_name_len, remaining_names_len;
 128         struct str_map {
 129                 char *old_str;
 130                 char *new_str;
 131         } reg_names_map[] = {
 132                 { "ccsr", "dbi" },
 133                 { "pf_ctrl", "ctrl" }
 134         };
 135         int off = -1, i;
 136
 137         if (IS_SVR_REV(get_svr(), 1, 0))
 138                 return 0;
 139
 140         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 141         while (off != -FDT_ERR_NOTFOUND) {
 142                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 143                             strlen("fsl,ls-pcie") + 1);
 144
 145                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 146                                                 &names_len);
 147                 if (!reg_names)
 148                         continue;
 149
 150                 reg_name = reg_names;
 151                 remaining_names_len = names_len - (reg_name - reg_names);
 152                 for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) {
 153                         old_name_len = strlen(reg_names_map[i].old_str);
 154                         new_name_len = strlen(reg_names_map[i].new_str);
 155                         if (memcmp(reg_name, reg_names_map[i].old_str,
 156                                    old_name_len) == 0) {
 157                                 /* first only leave required bytes for new_str
 158                                  * and copy rest of the string after it
 159                                  */
 160                                 memcpy(reg_name + new_name_len,
 161                                        reg_name + old_name_len,
 162                                        remaining_names_len - old_name_len);
 163                                 /* Now copy new_str */
 164                                 memcpy(reg_name, reg_names_map[i].new_str,
 165                                        new_name_len);
 166                                 names_len -= old_name_len;
 167                                 names_len += new_name_len;
 168                         }
 169
 170                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 171                         if (!reg_name)
 172                                 break;
 173
 174                         reg_name += 1;
 175
 176                         remaining_names_len = names_len -
 177                                               (reg_name - reg_names);
 178                 }
 179
 180                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 181                 off = fdt_node_offset_by_compatible(fdt, off,
 182                                                     "fsl,lx2160a-pcie");
 183         }
 184
 185         return 0;
 186 }
 187 #endif
 188
 189 #if defined(CONFIG_TARGET_LX2160AQDS)
 190 void esdhc_dspi_status_fixup(void *blob)
 191 {
 192         const char esdhc0_path[] = "/soc/esdhc@2140000";
 193         const char esdhc1_path[] = "/soc/esdhc@2150000";
 194         const char dspi0_path[] = "/soc/dspi@2100000";
 195         const char dspi1_path[] = "/soc/dspi@2110000";
 196         const char dspi2_path[] = "/soc/dspi@2120000";
 197
 198         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 199         u32 sdhc1_base_pmux;
 200         u32 sdhc2_base_pmux;
 201         u32 iic5_pmux;
 202
 203         /* Check RCW field sdhc1_base_pmux to enable/disable
 204          * esdhc0/dspi0 DT node
 205          */
 206         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 207                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 208         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 209
 210         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 211                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 212                                  sizeof("okay"), 1);
 213                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 214                                  sizeof("disabled"), 1);
 215         } else {
 216                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 217                                  sizeof("okay"), 1);
 218                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 219                                  sizeof("disabled"), 1);
 220         }
 221
 222         /* Check RCW field sdhc2_base_pmux to enable/disable
 223          * esdhc1/dspi1 DT node
 224          */
 225         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 226                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 227         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 228
 229         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 230                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 231                                  sizeof("okay"), 1);
 232                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 233                                  sizeof("disabled"), 1);
 234         } else {
 235                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 236                                  sizeof("okay"), 1);
 237                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 238                                  sizeof("disabled"), 1);
 239         }
 240
 241         /* Check RCW field IIC5 to enable dspi2 DT node */
 242         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 243                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 244         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 245
 246         if (iic5_pmux == IIC5_PMUX_SPI3) {
 247                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 248                                  sizeof("okay"), 1);
 249         }
 250 }
 251 #endif
 252
 253 int esdhc_status_fixup(void *blob, const char *compat)
 254 {
 255 #if defined(CONFIG_TARGET_LX2160AQDS)
 256         /* Enable esdhc and dspi DT nodes based on RCW fields */
 257         esdhc_dspi_status_fixup(blob);
 258 #else
 259         /* Enable both esdhc DT nodes for LX2160ARDB */
 260         do_fixup_by_compat(blob, compat, "status", "okay",
 261                            sizeof("okay"), 1);
 262 #endif
 263         return 0;
 264 }
 265
 266 #if defined(CONFIG_VID)
 267 int i2c_multiplexer_select_vid_channel(u8 channel)
 268 {
 269         return select_i2c_ch_pca9547(channel);
 270 }
 271
 272 int init_func_vid(void)
 273 {
 274         if (adjust_vdd(0) < 0)
 275                 printf("core voltage not adjusted\n");
 276
 277         return 0;
 278 }
 279 #endif
 280
 281 int checkboard(void)
 282 {
 283         enum boot_src src = get_boot_src();
 284         char buf[64];
 285         u8 sw;
 286 #ifdef CONFIG_TARGET_LX2160AQDS
 287         int clock;
 288         static const char *const freq[] = {"100", "125", "156.25",
 289                                            "161.13", "322.26", "", "", "",
 290                                            "", "", "", "", "", "", "",
 291                                            "100 separate SSCG"};
 292 #endif
 293
 294         cpu_name(buf);
 295 #ifdef CONFIG_TARGET_LX2160AQDS
 296         printf("Board: %s-QDS, ", buf);
 297 #else
 298         printf("Board: %s-RDB, ", buf);
 299 #endif
 300
 301         sw = QIXIS_READ(arch);
 302         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 303
 304         if (src == BOOT_SOURCE_SD_MMC) {
 305                 puts("SD\n");
 306         } else {
 307                 sw = QIXIS_READ(brdcfg[0]);
 308                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 309                 switch (sw) {
 310                 case 0:
 311                 case 4:
 312                         puts("FlexSPI DEV#0\n");
 313                         break;
 314                 case 1:
 315                         puts("FlexSPI DEV#1\n");
 316                         break;
 317                 case 2:
 318                 case 3:
 319                         puts("FlexSPI EMU\n");
 320                         break;
 321                 default:
 322                         printf("invalid setting, xmap: %d\n", sw);
 323                         break;
 324                 }
 325         }
 326 #ifdef CONFIG_TARGET_LX2160AQDS
 327         printf("FPGA: v%d (%s), build %d",
 328                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 329                (int)qixis_read_minor());
 330         /* the timestamp string contains "\n" at the end */
 331         printf(" on %s", qixis_read_time(buf));
 332
 333         puts("SERDES1 Reference : ");
 334         sw = QIXIS_READ(brdcfg[2]);
 335         clock = sw >> 4;
 336         printf("Clock1 = %sMHz ", freq[clock]);
 337         clock = sw & 0x0f;
 338         printf("Clock2 = %sMHz", freq[clock]);
 339
 340         sw = QIXIS_READ(brdcfg[3]);
 341         puts("\nSERDES2 Reference : ");
 342         clock = sw >> 4;
 343         printf("Clock1 = %sMHz ", freq[clock]);
 344         clock = sw & 0x0f;
 345         printf("Clock2 = %sMHz", freq[clock]);
 346
 347         sw = QIXIS_READ(brdcfg[12]);
 348         puts("\nSERDES3 Reference : ");
 349         clock = sw >> 4;
 350         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 351 #else
 352         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 353
 354         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 355         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 356         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 357 #endif
 358         return 0;
 359 }
 360
 361 #ifdef CONFIG_TARGET_LX2160AQDS
 362 /*
 363  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 364  */
 365 u8 qixis_esdhc_detect_quirk(void)
 366 {
 367         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 368          * SDHC1 Card ID:
 369          * Specifies the type of card installed in the SDHC1 adapter slot.
 370          * 000= (reserved)
 371          * 001= eMMC V4.5 adapter is installed.
 372          * 010= SD/MMC 3.3V adapter is installed.
 373          * 011= eMMC V4.4 adapter is installed.
 374          * 100= eMMC V5.0 adapter is installed.
 375          * 101= MMC card/Legacy (3.3V) adapter is installed.
 376          * 110= SDCard V2/V3 adapter installed.
 377          * 111= no adapter is installed.
 378          */
 379         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 380                  QIXIS_ESDHC_NO_ADAPTER);
 381 }
 382
 383 int config_board_mux(void)
 384 {
 385         u8 reg11, reg5, reg13;
 386         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 387         u32 sdhc1_base_pmux;
 388         u32 sdhc2_base_pmux;
 389         u32 iic5_pmux;
 390
 391         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 392          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 393          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 394          * Qixis and remote systems are isolated from the I2C1 bus.
 395          * Processor connections are still available.
 396          * SPI2 CS2_B controls EN25S64 SPI memory device.
 397          * SPI3 CS2_B controls EN25S64 SPI memory device.
 398          * EC2 connects to PHY #2 using RGMII protocol.
 399          * CLK_OUT connects to FPGA for clock measurement.
 400          */
 401
 402         reg5 = QIXIS_READ(brdcfg[5]);
 403         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 404         QIXIS_WRITE(brdcfg[5], reg5);
 405
 406         /* Check RCW field sdhc1_base_pmux
 407          * esdhc0 : sdhc1_base_pmux = 0
 408          * dspi0  : sdhc1_base_pmux = 2
 409          */
 410         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 411                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 412         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 413
 414         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 415                 reg11 = QIXIS_READ(brdcfg[11]);
 416                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 417                 QIXIS_WRITE(brdcfg[11], reg11);
 418         } else {
 419                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 420                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 421                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 422                  */
 423                 reg11 = QIXIS_READ(brdcfg[11]);
 424                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 425                 QIXIS_WRITE(brdcfg[11], reg11);
 426         }
 427
 428         /* Check RCW field sdhc2_base_pmux
 429          * esdhc1 : sdhc2_base_pmux = 0 (default)
 430          * dspi1  : sdhc2_base_pmux = 2
 431          */
 432         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 433                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 434         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 435
 436         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 437                 reg13 = QIXIS_READ(brdcfg[13]);
 438                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 439                 QIXIS_WRITE(brdcfg[13], reg13);
 440         } else {
 441                 reg13 = QIXIS_READ(brdcfg[13]);
 442                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 443                 QIXIS_WRITE(brdcfg[13], reg13);
 444         }
 445
 446         /* Check RCW field IIC5 to enable dspi2 DT nodei
 447          * dspi2: IIC5 = 3
 448          */
 449         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 450                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 451         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 452
 453         if (iic5_pmux == IIC5_PMUX_SPI3) {
 454                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 455                 reg11 = QIXIS_READ(brdcfg[11]);
 456                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 457                 QIXIS_WRITE(brdcfg[11], reg11);
 458
 459                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 460                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 461                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 462                  */
 463                 reg11 = QIXIS_READ(brdcfg[11]);
 464                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 465                 QIXIS_WRITE(brdcfg[11], reg11);
 466         } else {
 467                 /*  Routes {SDHC1_DAT4} to SDHC1 adapter slot */
 468                 reg11 = QIXIS_READ(brdcfg[11]);
 469                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 470                 QIXIS_WRITE(brdcfg[11], reg11);
 471
 472                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 473                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 474                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 475                  */
 476                 reg11 = QIXIS_READ(brdcfg[11]);
 477                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 478                 QIXIS_WRITE(brdcfg[11], reg11);
 479         }
 480
 481         return 0;
 482 }
 483 #elif defined(CONFIG_TARGET_LX2160ARDB)
 484 int config_board_mux(void)
 485 {
 486         u8 brdcfg;
 487
 488         brdcfg = QIXIS_READ(brdcfg[4]);
 489         /* The BRDCFG4 register controls general board configuration.
 490          *|-------------------------------------------|
 491          *|Field  | Function                          |
 492          *|-------------------------------------------|
 493          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 494          *|CAN_EN | 0= CAN transceivers are disabled. |
 495          *|       | 1= CAN transceivers are enabled.  |
 496          *|-------------------------------------------|
 497          */
 498         brdcfg |= BIT_MASK(5);
 499         QIXIS_WRITE(brdcfg[4], brdcfg);
 500
 501         return 0;
 502 }
 503 #else
 504 int config_board_mux(void)
 505 {
 506         return 0;
 507 }
 508 #endif
 509
 510 unsigned long get_board_sys_clk(void)
 511 {
 512 #ifdef CONFIG_TARGET_LX2160AQDS
 513         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 514
 515         switch (sysclk_conf & 0x03) {
 516         case QIXIS_SYSCLK_100:
 517                 return 100000000;
 518         case QIXIS_SYSCLK_125:
 519                 return 125000000;
 520         case QIXIS_SYSCLK_133:
 521                 return 133333333;
 522         }
 523         return 100000000;
 524 #else
 525         return 100000000;
 526 #endif
 527 }
 528
 529 unsigned long get_board_ddr_clk(void)
 530 {
 531 #ifdef CONFIG_TARGET_LX2160AQDS
 532         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 533
 534         switch ((ddrclk_conf & 0x30) >> 4) {
 535         case QIXIS_DDRCLK_100:
 536                 return 100000000;
 537         case QIXIS_DDRCLK_125:
 538                 return 125000000;
 539         case QIXIS_DDRCLK_133:
 540                 return 133333333;
 541         }
 542         return 100000000;
 543 #else
 544         return 100000000;
 545 #endif
 546 }
 547
 548 int board_init(void)
 549 {
 550 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 551         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 552 #endif
 553 #ifdef CONFIG_ENV_IS_NOWHERE
 554         gd->env_addr = (ulong)&default_environment[0];
 555 #endif
 556
 557         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 558
 559 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 560         /* invert AQR107 IRQ pins polarity */
 561         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 562 #endif
 563
 564 #ifdef CONFIG_FSL_CAAM
 565         sec_init();
 566 #endif
 567
 568         return 0;
 569 }
 570
 571 void detail_board_ddr_info(void)
 572 {
 573         int i;
 574         u64 ddr_size = 0;
 575
 576         puts("\nDDR    ");
 577         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 578                 ddr_size += gd->bd->bi_dram[i].size;
 579         print_size(ddr_size, "");
 580         print_ddr_info(0);
 581 }
 582
 583 #if defined(CONFIG_ARCH_MISC_INIT)
 584 int arch_misc_init(void)
 585 {
 586         config_board_mux();
 587
 588         return 0;
 589 }
 590 #endif
 591
 592 #ifdef CONFIG_FSL_MC_ENET
 593 extern int fdt_fixup_board_phy(void *fdt);
 594
 595 void fdt_fixup_board_enet(void *fdt)
 596 {
 597         int offset;
 598
 599         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 600
 601         if (offset < 0)
 602                 offset = fdt_path_offset(fdt, "/fsl-mc");
 603
 604         if (offset < 0) {
 605                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 606                        __func__, offset);
 607                 return;
 608         }
 609
 610         if (get_mc_boot_status() == 0 &&
 611             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 612                 fdt_status_okay(fdt, offset);
 613                 fdt_fixup_board_phy(fdt);
 614         } else {
 615                 fdt_status_fail(fdt, offset);
 616         }
 617 }
 618
 619 void board_quiesce_devices(void)
 620 {
 621         fsl_mc_ldpaa_exit(gd->bd);
 622 }
 623 #endif
 624
 625 #ifdef CONFIG_OF_BOARD_SETUP
 626
 627 int ft_board_setup(void *blob, bd_t *bd)
 628 {
 629         int i;
 630         u16 mc_memory_bank = 0;
 631
 632         u64 *base;
 633         u64 *size;
 634         u64 mc_memory_base = 0;
 635         u64 mc_memory_size = 0;
 636         u16 total_memory_banks;
 637
 638         ft_cpu_setup(blob, bd);
 639
 640         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 641
 642         if (mc_memory_base != 0)
 643                 mc_memory_bank++;
 644
 645         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 646
 647         base = calloc(total_memory_banks, sizeof(u64));
 648         size = calloc(total_memory_banks, sizeof(u64));
 649
 650         /* fixup DT for the three GPP DDR banks */
 651         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 652                 base[i] = gd->bd->bi_dram[i].start;
 653                 size[i] = gd->bd->bi_dram[i].size;
 654         }
 655
 656 #ifdef CONFIG_RESV_RAM
 657         /* reduce size if reserved memory is within this bank */
 658         if (gd->arch.resv_ram >= base[0] &&
 659             gd->arch.resv_ram < base[0] + size[0])
 660                 size[0] = gd->arch.resv_ram - base[0];
 661         else if (gd->arch.resv_ram >= base[1] &&
 662                  gd->arch.resv_ram < base[1] + size[1])
 663                 size[1] = gd->arch.resv_ram - base[1];
 664         else if (gd->arch.resv_ram >= base[2] &&
 665                  gd->arch.resv_ram < base[2] + size[2])
 666                 size[2] = gd->arch.resv_ram - base[2];
 667 #endif
 668
 669         if (mc_memory_base != 0) {
 670                 for (i = 0; i <= total_memory_banks; i++) {
 671                         if (base[i] == 0 && size[i] == 0) {
 672                                 base[i] = mc_memory_base;
 673                                 size[i] = mc_memory_size;
 674                                 break;
 675                         }
 676                 }
 677         }
 678
 679         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 680
 681 #ifdef CONFIG_USB
 682         fsl_fdt_fixup_dr_usb(blob, bd);
 683 #endif
 684
 685 #ifdef CONFIG_FSL_MC_ENET
 686         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 687         fdt_fixup_board_enet(blob);
 688 #endif
 689         fdt_fixup_icid(blob);
 690
 691         return 0;
 692 }
 693 #endif
 694
 695 void qixis_dump_switch(void)
 696 {
 697         int i, nr_of_cfgsw;
 698
 699         QIXIS_WRITE(cms[0], 0x00);
 700         nr_of_cfgsw = QIXIS_READ(cms[1]);
 701
 702         puts("DIP switch settings dump:\n");
 703         for (i = 1; i <= nr_of_cfgsw; i++) {
 704                 QIXIS_WRITE(cms[0], i);
 705                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 706         }
 707 }