board/freescale/lx2160a/eth_lx2160ardb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <net.h>
  10 #include <netdev.h>
  11 #include <malloc.h>
  12 #include <fsl_mdio.h>
  13 #include <miiphy.h>
  14 #include <phy.h>
  15 #include <fm_eth.h>
  16 #include <asm/io.h>
  17 #include <exports.h>
  18 #include <asm/arch/fsl_serdes.h>
  19 #include <fsl-mc/fsl_mc.h>
  20 #include <fsl-mc/ldpaa_wriop.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
  25 {
  26         int phy_reg;
  27         u32 phy_id;
  28
  29         phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  30         phy_id = (phy_reg & 0xffff) << 16;
  31
  32         phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  33         phy_id |= (phy_reg & 0xffff);
  34
  35         if (phy_id == PHY_UID_IN112525_S03)
  36                 return true;
  37         else
  38                 return false;
  39 }
  40
  41 int board_eth_init(bd_t *bis)
  42 {
  43 #if defined(CONFIG_FSL_MC_ENET)
  44         struct memac_mdio_info mdio_info;
  45         struct memac_mdio_controller *reg;
  46         int i, interface;
  47         struct mii_dev *dev;
  48         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  49         u32 srds_s1;
  50
  51         srds_s1 = in_le32(&gur->rcwsr[28]) &
  52                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  53         srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  54
  55         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  56         mdio_info.regs = reg;
  57         mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  58
  59         /* Register the EMI 1 */
  60         fm_memac_mdio_init(bis, &mdio_info);
  61
  62         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  63         mdio_info.regs = reg;
  64         mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  65
  66         /* Register the EMI 2 */
  67         fm_memac_mdio_init(bis, &mdio_info);
  68
  69         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  70         switch (srds_s1) {
  71         case 19:
  72                 wriop_set_phy_address(WRIOP1_DPMAC2, 0,
  73                                       CORTINA_PHY_ADDR1);
  74                 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
  75                                       AQR107_PHY_ADDR1);
  76                 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
  77                                       AQR107_PHY_ADDR2);
  78                 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
  79                         wriop_set_phy_address(WRIOP1_DPMAC5, 0,
  80                                               INPHI_PHY_ADDR1);
  81                         wriop_set_phy_address(WRIOP1_DPMAC6, 0,
  82                                               INPHI_PHY_ADDR1);
  83                 }
  84                 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
  85                                       RGMII_PHY_ADDR1);
  86                 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
  87                                       RGMII_PHY_ADDR2);
  88                 break;
  89
  90         case 18:
  91                 wriop_set_phy_address(WRIOP1_DPMAC7, 0,
  92                                       CORTINA_PHY_ADDR1);
  93                 wriop_set_phy_address(WRIOP1_DPMAC8, 0,
  94                                       CORTINA_PHY_ADDR1);
  95                 wriop_set_phy_address(WRIOP1_DPMAC9, 0,
  96                                       CORTINA_PHY_ADDR1);
  97                 wriop_set_phy_address(WRIOP1_DPMAC10, 0,
  98                                       CORTINA_PHY_ADDR1);
  99                 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
 100                                       AQR107_PHY_ADDR1);
 101                 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
 102                                       AQR107_PHY_ADDR2);
 103                 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
 104                         wriop_set_phy_address(WRIOP1_DPMAC5, 0,
 105                                               INPHI_PHY_ADDR1);
 106                         wriop_set_phy_address(WRIOP1_DPMAC6, 0,
 107                                               INPHI_PHY_ADDR1);
 108                 }
 109                 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
 110                                       RGMII_PHY_ADDR1);
 111                 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
 112                                       RGMII_PHY_ADDR2);
 113                 break;
 114
 115         default:
 116                 printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
 117                        srds_s1);
 118                 goto next;
 119         }
 120
 121         for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
 122                 interface = wriop_get_enet_if(i);
 123                 switch (interface) {
 124                 case PHY_INTERFACE_MODE_XGMII:
 125                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 126                         wriop_set_mdio(i, dev);
 127                         break;
 128                 case PHY_INTERFACE_MODE_25G_AUI:
 129                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 130                         wriop_set_mdio(i, dev);
 131                         break;
 132                 case PHY_INTERFACE_MODE_XLAUI:
 133                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 134                         wriop_set_mdio(i, dev);
 135                         break;
 136                 default:
 137                         break;
 138                 }
 139         }
 140         for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
 141                 interface = wriop_get_enet_if(i);
 142                 switch (interface) {
 143                 case PHY_INTERFACE_MODE_RGMII:
 144                 case PHY_INTERFACE_MODE_RGMII_ID:
 145                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 146                         wriop_set_mdio(i, dev);
 147                         break;
 148                 default:
 149                         break;
 150                 }
 151         }
 152
 153 next:
 154         cpu_eth_init(bis);
 155 #endif /* CONFIG_FSL_MC_ENET */
 156
 157 #ifdef CONFIG_PHY_AQUANTIA
 158         /*
 159          * Export functions to be used by AQ firmware
 160          * upload application
 161          */
 162         gd->jt->strcpy = strcpy;
 163         gd->jt->mdelay = mdelay;
 164         gd->jt->mdio_get_current_dev = mdio_get_current_dev;
 165         gd->jt->phy_find_by_mask = phy_find_by_mask;
 166         gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 167         gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 168 #endif
 169         return pci_eth_init(bis);
 170 }
 171
 172 #if defined(CONFIG_RESET_PHY_R)
 173 void reset_phy(void)
 174 {
 175 #if defined(CONFIG_FSL_MC_ENET)
 176         mc_env_boot();
 177 #endif
 178 }
 179 #endif /* CONFIG_RESET_PHY_R */
 180
 181 int fdt_fixup_board_phy(void *fdt)
 182 {
 183         int mdio_offset;
 184         int ret;
 185         struct mii_dev *dev;
 186
 187         ret = 0;
 188
 189         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 190         if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
 191                 mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
 192
 193                 if (mdio_offset < 0)
 194                         mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
 195
 196                 if (mdio_offset < 0) {
 197                         printf("mdio@0x8B9700 node not found in dts\n");
 198                         return mdio_offset;
 199                 }
 200
 201                 ret = fdt_setprop_string(fdt, mdio_offset, "status",
 202                                          "disabled");
 203                 if (ret) {
 204                         printf("Could not set disable mdio@0x8B97000 %s\n",
 205                                fdt_strerror(ret));
 206                         return ret;
 207                 }
 208         }
 209
 210         return ret;
 211 }