1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
20 #include <asm/arch/fsl_serdes.h>
21 #include <fsl-mc/fsl_mc.h>
22 #include <fsl-mc/ldpaa_wriop.h>
24 #include "../common/qixis.h"
26 DECLARE_GLOBAL_DATA_PTR;
30 #define EMI1 1 /* Mdio Bus 1 */
31 #define EMI2 2 /* Mdio Bus 2 */
33 #if defined(CONFIG_FSL_MC_ENET)
49 struct lx2160a_qds_mdio {
50 enum io_slot ioslot : 4;
52 struct mii_dev *realbus;
55 /* structure explaining the phy configuration on 8 lanes of a serdes*/
56 struct serdes_phy_config {
57 u8 serdes; /* serdes protocol */
60 /* -1 terminated array */
61 int phy_address[WRIOP_MAX_PHY_NUM + 1];
64 } phy_config[SRDS_MAX_LANES];
67 /* Table defining the phy configuration on 8 lanes of a serdes.
68 * Various assumptions have been made while defining this table.
69 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
70 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
71 * And also that this card is connected to IO Slot 1 (could have been connected
72 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
73 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
74 * used in serdes1 protocol 19 (could have selected MDIO 2)
75 * To override these settings "dpmac" environment variable can be used after
76 * defining "dpmac_override" in hwconfig environment variable.
77 * This table has limited serdes protocol entries. It can be expanded as per
80 static const struct serdes_phy_config serdes1_phy_config[] = {
81 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
83 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
85 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
87 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
89 {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
91 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
93 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
95 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
97 {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
99 {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
101 {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
103 {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
104 EMI1, IO_SLOT_2} } },
106 {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
108 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
109 EMI1, IO_SLOT_2} } },
110 {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
111 EMI1, IO_SLOT_1} } },
112 {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
114 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
115 EMI1, IO_SLOT_1} } },
116 {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
118 {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
120 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
122 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
123 EMI1, IO_SLOT_1} } },
124 {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
126 {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
128 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
130 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
132 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
133 EMI1, IO_SLOT_6} } },
134 {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
136 {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
140 static const struct serdes_phy_config serdes2_phy_config[] = {
144 {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
146 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
148 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
150 {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
152 {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
154 {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
155 EMI1, IO_SLOT_8} } },
158 static const struct serdes_phy_config serdes3_phy_config[] = {
164 const struct phy_config *get_phy_config(u8 serdes,
165 const struct serdes_phy_config *table,
170 for (i = 0; i < table_size; i++) {
171 if (table[i].serdes == serdes)
172 return table[i].phy_config;
178 /* BRDCFG4 controls EMI routing for the board.
180 * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
181 * EMI1 00= On-board PHY #1
182 * 01= On-board PHY #2
184 * 11= Slots 1..8 multiplexer and translator.
185 * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
194 * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
195 * EMI2 000= Slot #1 (secondary EMI)
196 * 001= Slot #2 (secondary EMI)
197 * 010= Slot #3 (secondary EMI)
198 * 011= Slot #4 (secondary EMI)
199 * 100= Slot #5 (secondary EMI)
200 * 101= Slot #6 (secondary EMI)
201 * 110= Slot #7 (secondary EMI)
202 * 111= Slot #8 (secondary EMI)
204 static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
206 switch (realbusnum) {
214 return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
218 return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
224 static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
226 u8 brdcfg4, mux_val, reg;
228 brdcfg4 = QIXIS_READ(brdcfg[4]);
230 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
232 switch (priv->realbusnum) {
234 brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
238 brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
244 QIXIS_WRITE(brdcfg[4], brdcfg4);
247 static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
248 int devad, int regnum)
250 struct lx2160a_qds_mdio *priv = bus->priv;
252 lx2160a_qds_mux_mdio(priv);
254 return priv->realbus->read(priv->realbus, addr, devad, regnum);
257 static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
258 int regnum, u16 value)
260 struct lx2160a_qds_mdio *priv = bus->priv;
262 lx2160a_qds_mux_mdio(priv);
264 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
267 static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
269 struct lx2160a_qds_mdio *priv = bus->priv;
271 return priv->realbus->reset(priv->realbus);
274 static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
276 struct lx2160a_qds_mdio *pmdio;
278 /*should be within MDIO_NAME_LEN*/
279 char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
281 if (realbusnum == EMI2) {
282 if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
283 printf("invalid ioslot %d\n", ioslot);
286 } else if (realbusnum == EMI1) {
287 if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
288 printf("invalid ioslot %d\n", ioslot);
292 printf("not supported real mdio bus %d\n", realbusnum);
296 if (ioslot == EMI1_RGMII1)
297 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
298 else if (ioslot == EMI1_RGMII2)
299 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
301 sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
303 bus = miiphy_get_dev_by_name(dummy_mdio_name);
310 printf("Failed to allocate %s bus\n", dummy_mdio_name);
314 pmdio = malloc(sizeof(*pmdio));
316 printf("Failed to allocate %s private data\n", dummy_mdio_name);
321 switch (realbusnum) {
324 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
328 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
332 if (!pmdio->realbus) {
333 printf("No real mdio bus num %d found\n", realbusnum);
339 pmdio->realbusnum = realbusnum;
340 pmdio->ioslot = ioslot;
341 bus->read = lx2160a_qds_mdio_read;
342 bus->write = lx2160a_qds_mdio_write;
343 bus->reset = lx2160a_qds_mdio_reset;
344 strcpy(bus->name, dummy_mdio_name);
347 if (!mdio_register(bus))
350 printf("No bus with name %s\n", dummy_mdio_name);
356 static inline void do_phy_config(const struct phy_config *phy_config)
359 int i, phy_num, phy_address;
361 for (i = 0; i < SRDS_MAX_LANES; i++) {
362 if (!phy_config[i].dpmacid)
366 phy_num < ARRAY_SIZE(phy_config[i].phy_address);
368 phy_address = phy_config[i].phy_address[phy_num];
369 if (phy_address == -1)
371 wriop_set_phy_address(phy_config[i].dpmacid,
372 phy_num, phy_address);
374 /*Register the muxing front-ends to the MDIO buses*/
375 bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
376 phy_config[i].ioslot);
378 printf("could not get bus for mdio %d ioslot %d\n",
379 phy_config[i].mdio_bus,
380 phy_config[i].ioslot);
382 wriop_set_mdio(phy_config[i].dpmacid, bus);
386 static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
391 u8 realbusnum, ioslot;
394 char *phystr = "phy00";
396 /*search phy in dpmac arg*/
397 for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
398 sprintf(phystr, "phy%d", phy_num + 1);
399 ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
401 /*look for phy instead of phy1*/
403 ret = hwconfig_subarg_f(arg_dpmacid, "phy",
409 if (len != 4 || strncmp(ret, "0x", 2))
410 printf("invalid phy format in %s variable.\n"
411 "specify phy%d for %s in hex format e.g. 0x12\n",
412 env_dpmac, phy_num + 1, arg_dpmacid);
414 wriop_set_phy_address(dpmac, phy_num,
415 simple_strtoul(ret, NULL, 16));
418 /*search mdio in dpmac arg*/
419 ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
421 realbusnum = *ret - '0';
423 realbusnum = EMI_NONE;
426 /*search io in dpmac arg*/
427 ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
431 ioslot = IO_SLOT_NONE;
432 /*Register the muxing front-ends to the MDIO buses*/
433 bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
435 printf("could not get bus for mdio %d ioslot %d\n",
438 wriop_set_mdio(dpmac, bus);
443 #endif /* !CONFIG_DM_ETH */
445 int board_eth_init(bd_t *bis)
447 #ifndef CONFIG_DM_ETH
448 #if defined(CONFIG_FSL_MC_ENET)
449 struct memac_mdio_info mdio_info;
450 struct memac_mdio_controller *regs;
454 char dpmacid[] = "dpmac00", srds[] = "00_00_00";
457 const struct phy_config *phy_config;
458 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
459 u32 srds_s1, srds_s2, srds_s3;
461 srds_s1 = in_le32(&gur->rcwsr[28]) &
462 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
463 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
465 srds_s2 = in_le32(&gur->rcwsr[28]) &
466 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
467 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
469 srds_s3 = in_le32(&gur->rcwsr[28]) &
470 FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
471 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
473 sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
475 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
476 mdio_info.regs = regs;
477 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
479 /*Register the EMI 1*/
480 fm_memac_mdio_init(bis, &mdio_info);
482 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
483 mdio_info.regs = regs;
484 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
486 /*Register the EMI 2*/
487 fm_memac_mdio_init(bis, &mdio_info);
489 /* "dpmac" environment variable can be used after
490 * defining "dpmac_override" in hwconfig environment variable.
492 if (hwconfig("dpmac_override")) {
493 env_dpmac = env_get("dpmac");
495 ret = hwconfig_arg_f("srds", &len, env_dpmac);
497 if (strncmp(ret, srds, strlen(srds))) {
498 printf("SERDES configuration changed.\n"
499 "previous: %.*s, current: %s.\n"
500 "update dpmac variable.\n",
501 (int)len, ret, srds);
504 printf("SERDES configuration not found.\n"
505 "Please add srds:%s in dpmac variable\n",
509 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
510 /* Look for dpmac1 to dpmac24(current max) arg
511 * in dpmac environment variable
513 sprintf(dpmacid, "dpmac%d", i);
514 ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
516 do_dpmac_config(i, dpmacid, env_dpmac);
519 printf("Warning: environment dpmac not found.\n"
520 "DPAA network interfaces may not work\n");
523 /*Look for phy config for serdes1 in phy config table*/
524 phy_config = get_phy_config(srds_s1, serdes1_phy_config,
525 ARRAY_SIZE(serdes1_phy_config));
527 printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
530 do_phy_config(phy_config);
532 phy_config = get_phy_config(srds_s2, serdes2_phy_config,
533 ARRAY_SIZE(serdes2_phy_config));
535 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
538 do_phy_config(phy_config);
540 phy_config = get_phy_config(srds_s3, serdes3_phy_config,
541 ARRAY_SIZE(serdes3_phy_config));
543 printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
546 do_phy_config(phy_config);
550 if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
551 wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
552 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
554 printf("could not get bus for RGMII1\n");
556 wriop_set_mdio(WRIOP1_DPMAC17, bus);
559 if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
560 wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
561 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
563 printf("could not get bus for RGMII2\n");
565 wriop_set_mdio(WRIOP1_DPMAC18, bus);
569 #endif /* CONFIG_FMAN_ENET */
570 #endif /* !CONFIG_DM_ETH */
572 #ifdef CONFIG_PHY_AQUANTIA
574 * Export functions to be used by AQ firmware
577 gd->jt->strcpy = strcpy;
578 gd->jt->mdelay = mdelay;
579 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
580 gd->jt->phy_find_by_mask = phy_find_by_mask;
581 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
582 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
588 return pci_eth_init(bis);
592 #if defined(CONFIG_RESET_PHY_R)
595 #if defined(CONFIG_FSL_MC_ENET)
599 #endif /* CONFIG_RESET_PHY_R */
601 #ifndef CONFIG_DM_ETH
602 #if defined(CONFIG_FSL_MC_ENET)
603 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
607 char dpmac_str[] = "dpmacs@00";
608 const char *phy_string;
610 offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
613 offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
616 printf("dpmacs node not found in device tree\n");
620 sprintf(dpmac_str, "dpmac@%x", dpmac_id);
621 debug("dpmac_str = %s\n", dpmac_str);
623 offset = fdt_subnode_offset(fdt, offset, dpmac_str);
625 printf("%s node not found in device tree\n", dpmac_str);
629 phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
630 if (is_backplane_mode(phy_string)) {
631 /* Backplane KR mode: skip fixups */
632 printf("Interface %d in backplane KR mode\n", dpmac_id);
636 ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
638 printf("%d@%s %d\n", __LINE__, __func__, ret);
640 phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
641 ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
644 printf("%d@%s %d\n", __LINE__, __func__, ret);
649 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
651 char mdio_ioslot_str[] = "mdio@00";
652 struct lx2160a_qds_mdio *priv;
657 /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
658 if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
659 strlen("LX2160A_QDS_MDIO")))
662 /*Get the real MDIO bus num and ioslot info from bus's priv data*/
663 priv = mii_dev->priv;
665 debug("real_bus_num = %d, ioslot = %d\n",
666 priv->realbusnum, priv->ioslot);
668 if (priv->realbusnum == EMI1)
669 reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
671 reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
673 offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
675 printf("mdio@%llx node not found in device tree\n", reg);
679 phandle = fdt_get_phandle(fdt, offset);
680 phandle = cpu_to_fdt32(phandle);
681 offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
684 printf("mdio-mux-%d node not found in device tree\n",
685 priv->realbusnum == EMI1 ? 1 : 2);
689 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
690 if (priv->realbusnum == EMI1)
691 mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
693 mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
694 sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
696 offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
698 printf("%s node not found in device tree\n", mdio_ioslot_str);
705 int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
706 struct phy_device *phy_dev, int phandle)
708 char phy_node_name[] = "ethernet-phy@00";
709 char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
712 sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
713 debug("phy_node_name = %s\n", phy_node_name);
715 *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
716 if (*subnodeoffset <= 0) {
717 printf("Could not add subnode %s inside node %s err = %s\n",
718 phy_node_name, fdt_get_name(fdt, offset, NULL),
719 fdt_strerror(*subnodeoffset));
720 return *subnodeoffset;
723 sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
724 phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
725 debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
727 ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
728 phy_id_compatible_str);
730 printf("%d@%s %d\n", __LINE__, __func__, ret);
734 if (phy_dev->is_c45) {
735 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
736 "ethernet-phy-ieee802.3-c45");
738 printf("%d@%s %d\n", __LINE__, __func__, ret);
742 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
743 "ethernet-phy-ieee802.3-c22");
745 printf("%d@%s %d\n", __LINE__, __func__, ret);
750 ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
752 printf("%d@%s %d\n", __LINE__, __func__, ret);
756 ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
758 printf("%d@%s %d\n", __LINE__, __func__, ret);
764 fdt_del_node(fdt, *subnodeoffset);
769 int fdt_fixup_board_phy(void *fdt)
771 int fpga_offset, offset, subnodeoffset;
772 struct mii_dev *mii_dev;
773 struct list_head *mii_devs, *entry;
774 int ret, dpmac_id, phandle, i;
775 struct phy_device *phy_dev;
776 char ethname[ETH_NAME_LEN];
777 phy_interface_t phy_iface;
780 /* we know FPGA is connected to i2c0, therefore search path directly,
781 * instead of compatible property, as it saves time
783 fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
786 fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
788 if (fpga_offset < 0) {
789 printf("i2c@2000000/fpga node not found in device tree\n");
793 phandle = fdt_alloc_phandle(fdt);
794 mii_devs = mdio_get_list_head();
796 list_for_each(entry, mii_devs) {
797 mii_dev = list_entry(entry, struct mii_dev, link);
798 debug("mii_dev name : %s\n", mii_dev->name);
799 offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
803 // Look for phy devices attached to MDIO bus muxing front end
804 // and create their entries with compatible being the device id
805 for (i = 0; i < PHY_MAX_ADDR; i++) {
806 phy_dev = mii_dev->phymap[i];
810 // TODO: use sscanf instead of loop
811 dpmac_id = WRIOP1_DPMAC1;
812 while (dpmac_id < NUM_WRIOP_PORTS) {
813 phy_iface = wriop_get_enet_if(dpmac_id);
814 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
816 phy_string_for_interface(phy_iface));
817 if (strcmp(ethname, phy_dev->dev->name) == 0)
821 if (dpmac_id == NUM_WRIOP_PORTS)
823 ret = fdt_create_phy_node(fdt, offset, i,
829 ret = fdt_fixup_dpmac_phy_handle(fdt,
832 fdt_del_node(fdt, subnodeoffset);
835 /* calculate offset again as new node addition may have
838 offset = fdt_get_ioslot_offset(fdt, mii_dev,
849 #endif // CONFIG_FSL_MC_ENET