board/freescale/ls2080aqds/eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <env.h>
   8 #include <log.h>
   9 #include <net.h>
  10 #include <netdev.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <hwconfig.h>
  14 #include <fsl_mdio.h>
  15 #include <malloc.h>
  16 #include <fm_eth.h>
  17 #include <i2c.h>
  18 #include <miiphy.h>
  19 #include <fsl-mc/fsl_mc.h>
  20 #include <fsl-mc/ldpaa_wriop.h>
  21 #include <linux/delay.h>
  22
  23 #include "../common/qixis.h"
  24
  25 #include "ls2080aqds_qixis.h"
  26
  27 #define MC_BOOT_ENV_VAR "mcinitcmd"
  28
  29 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  30  /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  31  *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
  32  *   Bank 2 -> Lanes A,B, C, D, E, F, G, H
  33  */
  34
  35  /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
  36   * means that the mapping must be determined dynamically, or that the lane
  37   * maps to something other than a board slot.
  38   */
  39
  40 static u8 lane_to_slot_fsm1[] = {
  41         0, 0, 0, 0, 0, 0, 0, 0
  42 };
  43
  44 static u8 lane_to_slot_fsm2[] = {
  45         0, 0, 0, 0, 0, 0, 0, 0
  46 };
  47
  48 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  49  * housed.
  50  */
  51
  52 static int xqsgii_riser_phy_addr[] = {
  53         XQSGMII_CARD_PHY1_PORT0_ADDR,
  54         XQSGMII_CARD_PHY2_PORT0_ADDR,
  55         XQSGMII_CARD_PHY3_PORT0_ADDR,
  56         XQSGMII_CARD_PHY4_PORT0_ADDR,
  57         XQSGMII_CARD_PHY3_PORT2_ADDR,
  58         XQSGMII_CARD_PHY1_PORT2_ADDR,
  59         XQSGMII_CARD_PHY4_PORT2_ADDR,
  60         XQSGMII_CARD_PHY2_PORT2_ADDR,
  61 };
  62
  63 static int sgmii_riser_phy_addr[] = {
  64         SGMII_CARD_PORT1_PHY_ADDR,
  65         SGMII_CARD_PORT2_PHY_ADDR,
  66         SGMII_CARD_PORT3_PHY_ADDR,
  67         SGMII_CARD_PORT4_PHY_ADDR,
  68 };
  69
  70 /* Slot2 does not have EMI connections */
  71 #define EMI_NONE        0xFF
  72 #define EMI1_SLOT1      0
  73 #define EMI1_SLOT2      1
  74 #define EMI1_SLOT3      2
  75 #define EMI1_SLOT4      3
  76 #define EMI1_SLOT5      4
  77 #define EMI1_SLOT6      5
  78 #define EMI2            6
  79 #define SFP_TX          0
  80
  81 static const char * const mdio_names[] = {
  82         "LS2080A_QDS_MDIO0",
  83         "LS2080A_QDS_MDIO1",
  84         "LS2080A_QDS_MDIO2",
  85         "LS2080A_QDS_MDIO3",
  86         "LS2080A_QDS_MDIO4",
  87         "LS2080A_QDS_MDIO5",
  88         DEFAULT_WRIOP_MDIO2_NAME,
  89 };
  90
  91 struct ls2080a_qds_mdio {
  92         u8 muxval;
  93         struct mii_dev *realbus;
  94 };
  95
  96 struct reg_pair {
  97         uint addr;
  98         u8 *val;
  99 };
 100
 101 static void sgmii_configure_repeater(int serdes_port)
 102 {
 103         struct mii_dev *bus;
 104         uint8_t a = 0xf;
 105         int i, j, k, ret;
 106         int dpmac_id = 0, dpmac, mii_bus = 0;
 107         unsigned short value;
 108         char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
 109         uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
 110
 111         uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
 112         uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 113         uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 114         uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 115
 116         u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
 117         struct reg_pair reg_pair[10] = {
 118                         {6, &reg_val[0]}, {4, &reg_val[1]},
 119                         {8, &reg_val[2]}, {0xf, NULL},
 120                         {0x11, NULL}, {0x16, NULL},
 121                         {0x18, NULL}, {0x23, &reg_val[3]},
 122                         {0x2d, &reg_val[4]}, {4, &reg_val[5]},
 123         };
 124
 125         int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
 126 #ifdef CONFIG_DM_I2C
 127         struct udevice *udev;
 128 #endif
 129
 130         /* Set I2c to Slot 1 */
 131 #ifndef CONFIG_DM_I2C
 132         ret = i2c_write(0x77, 0, 0, &a, 1);
 133 #else
 134         ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
 135         if (!ret)
 136                 ret = dm_i2c_write(udev, 0, &a, 1);
 137 #endif
 138         if (ret)
 139                 goto error;
 140
 141         for (dpmac = 0; dpmac < 8; dpmac++) {
 142                 /* Check the PHY status */
 143                 switch (serdes_port) {
 144                 case 1:
 145                         mii_bus = 0;
 146                         dpmac_id = dpmac + 1;
 147                         break;
 148                 case 2:
 149                         mii_bus = 1;
 150                         dpmac_id = dpmac + 9;
 151                         a = 0xb;
 152 #ifndef CONFIG_DM_I2C
 153                         ret = i2c_write(0x76, 0, 0, &a, 1);
 154 #else
 155                         ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
 156                         if (!ret)
 157                                 ret = dm_i2c_write(udev, 0, &a, 1);
 158 #endif
 159                         if (ret)
 160                                 goto error;
 161                         break;
 162                 }
 163
 164                 ret = miiphy_set_current_dev(dev[mii_bus]);
 165                 if (ret > 0)
 166                         goto error;
 167
 168                 bus = mdio_get_current_dev();
 169                 debug("Reading from bus %s\n", bus->name);
 170
 171                 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
 172                                    3);
 173                 if (ret > 0)
 174                         goto error;
 175
 176                 mdelay(10);
 177                 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
 178                                   &value);
 179                 if (ret > 0)
 180                         goto error;
 181
 182                 mdelay(10);
 183
 184                 if ((value & 0xfff) == 0x401) {
 185                         printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
 186                         miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
 187                                      0x1f, 0);
 188                         continue;
 189                 }
 190
 191                 for (i = 0; i < 4; i++) {
 192                         for (j = 0; j < 4; j++) {
 193                                 reg_pair[3].val = &ch_a_eq[i];
 194                                 reg_pair[4].val = &ch_a_ctl2[j];
 195                                 reg_pair[5].val = &ch_b_eq[i];
 196                                 reg_pair[6].val = &ch_b_ctl2[j];
 197
 198                                 for (k = 0; k < 10; k++) {
 199 #ifndef CONFIG_DM_I2C
 200                                         ret = i2c_write(i2c_addr[dpmac],
 201                                                         reg_pair[k].addr,
 202                                                         1, reg_pair[k].val, 1);
 203 #else
 204                                         ret = i2c_get_chip_for_busnum(0,
 205                                                             i2c_addr[dpmac],
 206                                                             1, &udev);
 207                                         if (!ret)
 208                                                 ret = dm_i2c_write(udev,
 209                                                           reg_pair[k].addr,
 210                                                           reg_pair[k].val, 1);
 211 #endif
 212                                         if (ret)
 213                                                 goto error;
 214                                 }
 215
 216                                 mdelay(100);
 217                                 ret = miiphy_read(dev[mii_bus],
 218                                                   riser_phy_addr[dpmac],
 219                                                   0x11, &value);
 220                                 if (ret > 0)
 221                                         goto error;
 222
 223                                 mdelay(100);
 224                                 ret = miiphy_read(dev[mii_bus],
 225                                                   riser_phy_addr[dpmac],
 226                                                   0x11, &value);
 227                                 if (ret > 0)
 228                                         goto error;
 229
 230                                 if ((value & 0xfff) == 0x401) {
 231                                         printf("DPMAC %d :PHY is configured ",
 232                                                dpmac_id);
 233                                         printf("after setting repeater 0x%x\n",
 234                                                value);
 235                                         i = 5;
 236                                         j = 5;
 237                                 } else {
 238                                         printf("DPMAC %d :PHY is failed to ",
 239                                                dpmac_id);
 240                                         printf("configure the repeater 0x%x\n",
 241                                                value);
 242                                 }
 243                         }
 244                 }
 245                 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
 246         }
 247 error:
 248         if (ret)
 249                 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
 250         return;
 251 }
 252
 253 static void qsgmii_configure_repeater(int dpmac)
 254 {
 255         uint8_t a = 0xf;
 256         int i, j, k;
 257         int i2c_phy_addr = 0;
 258         int phy_addr = 0;
 259         int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
 260
 261         uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
 262         uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 263         uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 264         uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 265
 266         u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
 267         struct reg_pair reg_pair[10] = {
 268                 {6, &reg_val[0]}, {4, &reg_val[1]},
 269                 {8, &reg_val[2]}, {0xf, NULL},
 270                 {0x11, NULL}, {0x16, NULL},
 271                 {0x18, NULL}, {0x23, &reg_val[3]},
 272                 {0x2d, &reg_val[4]}, {4, &reg_val[5]},
 273         };
 274
 275         const char *dev = "LS2080A_QDS_MDIO0";
 276         int ret = 0;
 277         unsigned short value;
 278 #ifdef CONFIG_DM_I2C
 279         struct udevice *udev;
 280 #endif
 281
 282         /* Set I2c to Slot 1 */
 283 #ifndef CONFIG_DM_I2C
 284         ret = i2c_write(0x77, 0, 0, &a, 1);
 285 #else
 286         ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
 287         if (!ret)
 288                 ret = dm_i2c_write(udev, 0, &a, 1);
 289 #endif
 290         if (ret)
 291                 goto error;
 292
 293         switch (dpmac) {
 294         case 1:
 295         case 2:
 296         case 3:
 297         case 4:
 298                 i2c_phy_addr = i2c_addr[0];
 299                 phy_addr = 0;
 300                 break;
 301
 302         case 5:
 303         case 6:
 304         case 7:
 305         case 8:
 306                 i2c_phy_addr = i2c_addr[1];
 307                 phy_addr = 4;
 308                 break;
 309
 310         case 9:
 311         case 10:
 312         case 11:
 313         case 12:
 314                 i2c_phy_addr = i2c_addr[2];
 315                 phy_addr = 8;
 316                 break;
 317
 318         case 13:
 319         case 14:
 320         case 15:
 321         case 16:
 322                 i2c_phy_addr = i2c_addr[3];
 323                 phy_addr = 0xc;
 324                 break;
 325         }
 326
 327         /* Check the PHY status */
 328         ret = miiphy_set_current_dev(dev);
 329         ret = miiphy_write(dev, phy_addr, 0x1f, 3);
 330         mdelay(10);
 331         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 332         mdelay(10);
 333         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 334         mdelay(10);
 335         if ((value & 0xf) == 0xf) {
 336                 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
 337                 return;
 338         }
 339
 340         for (i = 0; i < 4; i++) {
 341                 for (j = 0; j < 4; j++) {
 342                         reg_pair[3].val = &ch_a_eq[i];
 343                         reg_pair[4].val = &ch_a_ctl2[j];
 344                         reg_pair[5].val = &ch_b_eq[i];
 345                         reg_pair[6].val = &ch_b_ctl2[j];
 346
 347                         for (k = 0; k < 10; k++) {
 348 #ifndef CONFIG_DM_I2C
 349                                 ret = i2c_write(i2c_phy_addr,
 350                                                 reg_pair[k].addr,
 351                                                 1, reg_pair[k].val, 1);
 352 #else
 353                                 ret = i2c_get_chip_for_busnum(0,
 354                                                               i2c_phy_addr,
 355                                                               1, &udev);
 356                                 if (!ret)
 357                                         ret = dm_i2c_write(udev,
 358                                                            reg_pair[k].addr,
 359                                                            reg_pair[k].val, 1);
 360 #endif
 361                                 if (ret)
 362                                         goto error;
 363                         }
 364
 365                         mdelay(100);
 366                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 367                         if (ret > 0)
 368                                 goto error;
 369                         mdelay(1);
 370                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 371                         if (ret > 0)
 372                                 goto error;
 373                         mdelay(10);
 374                         if ((value & 0xf) == 0xf) {
 375                                 printf("DPMAC %d :PHY is ..... Configured\n",
 376                                        dpmac);
 377                                 return;
 378                         }
 379                 }
 380         }
 381 error:
 382         printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
 383         return;
 384 }
 385
 386 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
 387 {
 388         return mdio_names[muxval];
 389 }
 390
 391 struct mii_dev *mii_dev_for_muxval(u8 muxval)
 392 {
 393         struct mii_dev *bus;
 394         const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
 395
 396         if (!name) {
 397                 printf("No bus for muxval %x\n", muxval);
 398                 return NULL;
 399         }
 400
 401         bus = miiphy_get_dev_by_name(name);
 402
 403         if (!bus) {
 404                 printf("No bus by name %s\n", name);
 405                 return NULL;
 406         }
 407
 408         return bus;
 409 }
 410
 411 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
 412 {
 413         u8 brdcfg9;
 414
 415         brdcfg9 = QIXIS_READ(brdcfg[9]);
 416         brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
 417         brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
 418         QIXIS_WRITE(brdcfg[9], brdcfg9);
 419 }
 420
 421 static void ls2080a_qds_mux_mdio(u8 muxval)
 422 {
 423         u8 brdcfg4;
 424
 425         if (muxval <= 5) {
 426                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 427                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 428                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 429                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 430         }
 431 }
 432
 433 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
 434                                  int devad, int regnum)
 435 {
 436         struct ls2080a_qds_mdio *priv = bus->priv;
 437
 438         ls2080a_qds_mux_mdio(priv->muxval);
 439
 440         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 441 }
 442
 443 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 444                                   int regnum, u16 value)
 445 {
 446         struct ls2080a_qds_mdio *priv = bus->priv;
 447
 448         ls2080a_qds_mux_mdio(priv->muxval);
 449
 450         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 451 }
 452
 453 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
 454 {
 455         struct ls2080a_qds_mdio *priv = bus->priv;
 456
 457         return priv->realbus->reset(priv->realbus);
 458 }
 459
 460 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
 461 {
 462         struct ls2080a_qds_mdio *pmdio;
 463         struct mii_dev *bus = mdio_alloc();
 464
 465         if (!bus) {
 466                 printf("Failed to allocate ls2080a_qds MDIO bus\n");
 467                 return -1;
 468         }
 469
 470         pmdio = malloc(sizeof(*pmdio));
 471         if (!pmdio) {
 472                 printf("Failed to allocate ls2080a_qds private data\n");
 473                 free(bus);
 474                 return -1;
 475         }
 476
 477         bus->read = ls2080a_qds_mdio_read;
 478         bus->write = ls2080a_qds_mdio_write;
 479         bus->reset = ls2080a_qds_mdio_reset;
 480         strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
 481
 482         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 483
 484         if (!pmdio->realbus) {
 485                 printf("No bus with name %s\n", realbusname);
 486                 free(bus);
 487                 free(pmdio);
 488                 return -1;
 489         }
 490
 491         pmdio->muxval = muxval;
 492         bus->priv = pmdio;
 493
 494         return mdio_register(bus);
 495 }
 496
 497 /*
 498  * Initialize the dpmac_info array.
 499  *
 500  */
 501 static void initialize_dpmac_to_slot(void)
 502 {
 503         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 504         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 505                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 506                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 507         int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
 508                                 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
 509                 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
 510
 511         char *env_hwconfig;
 512         env_hwconfig = env_get("hwconfig");
 513
 514         switch (serdes1_prtcl) {
 515         case 0x07:
 516         case 0x09:
 517         case 0x33:
 518                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 519                        serdes1_prtcl);
 520                 lane_to_slot_fsm1[0] = EMI1_SLOT1;
 521                 lane_to_slot_fsm1[1] = EMI1_SLOT1;
 522                 lane_to_slot_fsm1[2] = EMI1_SLOT1;
 523                 lane_to_slot_fsm1[3] = EMI1_SLOT1;
 524                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 525                         lane_to_slot_fsm1[4] = EMI1_SLOT1;
 526                         lane_to_slot_fsm1[5] = EMI1_SLOT1;
 527                         lane_to_slot_fsm1[6] = EMI1_SLOT1;
 528                         lane_to_slot_fsm1[7] = EMI1_SLOT1;
 529                 } else {
 530                         lane_to_slot_fsm1[4] = EMI1_SLOT2;
 531                         lane_to_slot_fsm1[5] = EMI1_SLOT2;
 532                         lane_to_slot_fsm1[6] = EMI1_SLOT2;
 533                         lane_to_slot_fsm1[7] = EMI1_SLOT2;
 534                 }
 535                 break;
 536
 537         case 0x39:
 538                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 539                        serdes1_prtcl);
 540                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 541                         lane_to_slot_fsm1[0] = EMI1_SLOT3;
 542                         lane_to_slot_fsm1[1] = EMI1_SLOT3;
 543                         lane_to_slot_fsm1[2] = EMI1_SLOT3;
 544                         lane_to_slot_fsm1[3] = EMI_NONE;
 545                 } else {
 546                         lane_to_slot_fsm1[0] = EMI_NONE;
 547                         lane_to_slot_fsm1[1] = EMI_NONE;
 548                         lane_to_slot_fsm1[2] = EMI_NONE;
 549                         lane_to_slot_fsm1[3] = EMI_NONE;
 550                 }
 551                 lane_to_slot_fsm1[4] = EMI1_SLOT3;
 552                 lane_to_slot_fsm1[5] = EMI1_SLOT3;
 553                 lane_to_slot_fsm1[6] = EMI1_SLOT3;
 554                 lane_to_slot_fsm1[7] = EMI_NONE;
 555                 break;
 556
 557         case 0x4D:
 558                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 559                        serdes1_prtcl);
 560                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 561                         lane_to_slot_fsm1[0] = EMI1_SLOT3;
 562                         lane_to_slot_fsm1[1] = EMI1_SLOT3;
 563                         lane_to_slot_fsm1[2] = EMI_NONE;
 564                         lane_to_slot_fsm1[3] = EMI_NONE;
 565                 } else {
 566                         lane_to_slot_fsm1[0] = EMI_NONE;
 567                         lane_to_slot_fsm1[1] = EMI_NONE;
 568                         lane_to_slot_fsm1[2] = EMI_NONE;
 569                         lane_to_slot_fsm1[3] = EMI_NONE;
 570                 }
 571                 lane_to_slot_fsm1[4] = EMI1_SLOT3;
 572                 lane_to_slot_fsm1[5] = EMI1_SLOT3;
 573                 lane_to_slot_fsm1[6] = EMI_NONE;
 574                 lane_to_slot_fsm1[7] = EMI_NONE;
 575                 break;
 576
 577         case 0x2A:
 578         case 0x4B:
 579         case 0x4C:
 580                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 581                        serdes1_prtcl);
 582                 break;
 583         default:
 584                 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
 585                        __func__, serdes1_prtcl);
 586                 break;
 587         }
 588
 589         switch (serdes2_prtcl) {
 590         case 0x07:
 591         case 0x08:
 592         case 0x09:
 593         case 0x49:
 594                 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
 595                        serdes2_prtcl);
 596                 lane_to_slot_fsm2[0] = EMI1_SLOT4;
 597                 lane_to_slot_fsm2[1] = EMI1_SLOT4;
 598                 lane_to_slot_fsm2[2] = EMI1_SLOT4;
 599                 lane_to_slot_fsm2[3] = EMI1_SLOT4;
 600
 601                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 602                         lane_to_slot_fsm2[4] = EMI1_SLOT4;
 603                         lane_to_slot_fsm2[5] = EMI1_SLOT4;
 604                         lane_to_slot_fsm2[6] = EMI1_SLOT4;
 605                         lane_to_slot_fsm2[7] = EMI1_SLOT4;
 606                 } else {
 607                         /* No MDIO physical connection */
 608                         lane_to_slot_fsm2[4] = EMI1_SLOT6;
 609                         lane_to_slot_fsm2[5] = EMI1_SLOT6;
 610                         lane_to_slot_fsm2[6] = EMI1_SLOT6;
 611                         lane_to_slot_fsm2[7] = EMI1_SLOT6;
 612                 }
 613                 break;
 614
 615         case 0x47:
 616                 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
 617                        serdes2_prtcl);
 618                 lane_to_slot_fsm2[0] = EMI_NONE;
 619                 lane_to_slot_fsm2[1] = EMI1_SLOT5;
 620                 lane_to_slot_fsm2[2] = EMI1_SLOT5;
 621                 lane_to_slot_fsm2[3] = EMI1_SLOT5;
 622
 623                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 624                         lane_to_slot_fsm2[4] = EMI_NONE;
 625                         lane_to_slot_fsm2[5] = EMI1_SLOT5;
 626                         lane_to_slot_fsm2[6] = EMI1_SLOT5;
 627                         lane_to_slot_fsm2[7] = EMI1_SLOT5;
 628                 }
 629                 break;
 630
 631         case 0x57:
 632                 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
 633                        serdes2_prtcl);
 634                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 635                         lane_to_slot_fsm2[0] = EMI_NONE;
 636                         lane_to_slot_fsm2[1] = EMI_NONE;
 637                         lane_to_slot_fsm2[2] = EMI_NONE;
 638                         lane_to_slot_fsm2[3] = EMI_NONE;
 639                 }
 640                 lane_to_slot_fsm2[4] = EMI_NONE;
 641                 lane_to_slot_fsm2[5] = EMI_NONE;
 642                 lane_to_slot_fsm2[6] = EMI1_SLOT5;
 643                 lane_to_slot_fsm2[7] = EMI1_SLOT5;
 644                 break;
 645
 646         default:
 647                 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
 648                        __func__ , serdes2_prtcl);
 649                 break;
 650         }
 651 }
 652
 653 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
 654 {
 655         int lane, slot;
 656         struct mii_dev *bus;
 657         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 658         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 659                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 660                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 661         int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
 662                                 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
 663                 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
 664
 665         int *riser_phy_addr;
 666         char *env_hwconfig = env_get("hwconfig");
 667
 668         if (hwconfig_f("xqsgmii", env_hwconfig))
 669                 riser_phy_addr = &xqsgii_riser_phy_addr[0];
 670         else
 671                 riser_phy_addr = &sgmii_riser_phy_addr[0];
 672
 673         if (dpmac_id > WRIOP1_DPMAC9)
 674                 goto serdes2;
 675
 676         switch (serdes1_prtcl) {
 677         case 0x07:
 678         case 0x39:
 679         case 0x4D:
 680                 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
 681
 682                 slot = lane_to_slot_fsm1[lane];
 683
 684                 switch (++slot) {
 685                 case 1:
 686                         /* Slot housing a SGMII riser card? */
 687                         wriop_set_phy_address(dpmac_id, 0,
 688                                               riser_phy_addr[dpmac_id - 1]);
 689                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
 690                         bus = mii_dev_for_muxval(EMI1_SLOT1);
 691                         wriop_set_mdio(dpmac_id, bus);
 692                         break;
 693                 case 2:
 694                         /* Slot housing a SGMII riser card? */
 695                         wriop_set_phy_address(dpmac_id, 0,
 696                                               riser_phy_addr[dpmac_id - 1]);
 697                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
 698                         bus = mii_dev_for_muxval(EMI1_SLOT2);
 699                         wriop_set_mdio(dpmac_id, bus);
 700                         break;
 701                 case 3:
 702                         if (slot == EMI_NONE)
 703                                 return;
 704                         if (serdes1_prtcl == 0x39) {
 705                                 wriop_set_phy_address(dpmac_id, 0,
 706                                         riser_phy_addr[dpmac_id - 2]);
 707                                 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
 708                                                                 env_hwconfig))
 709                                         wriop_set_phy_address(dpmac_id, 0,
 710                                                 riser_phy_addr[dpmac_id - 3]);
 711                         } else {
 712                                 wriop_set_phy_address(dpmac_id, 0,
 713                                         riser_phy_addr[dpmac_id - 2]);
 714                                 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
 715                                                                 env_hwconfig))
 716                                         wriop_set_phy_address(dpmac_id, 0,
 717                                                 riser_phy_addr[dpmac_id - 3]);
 718                         }
 719                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
 720                         bus = mii_dev_for_muxval(EMI1_SLOT3);
 721                         wriop_set_mdio(dpmac_id, bus);
 722                         break;
 723                 case 4:
 724                         break;
 725                 case 5:
 726                         break;
 727                 case 6:
 728                         break;
 729                 }
 730         break;
 731         default:
 732                 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
 733                        __func__ , serdes1_prtcl);
 734         break;
 735         }
 736
 737 serdes2:
 738         switch (serdes2_prtcl) {
 739         case 0x07:
 740         case 0x08:
 741         case 0x49:
 742         case 0x47:
 743         case 0x57:
 744                 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
 745                                                         (dpmac_id - 9));
 746                 slot = lane_to_slot_fsm2[lane];
 747
 748                 switch (++slot) {
 749                 case 1:
 750                         break;
 751                 case 3:
 752                         break;
 753                 case 4:
 754                         /* Slot housing a SGMII riser card? */
 755                         wriop_set_phy_address(dpmac_id, 0,
 756                                               riser_phy_addr[dpmac_id - 9]);
 757                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
 758                         bus = mii_dev_for_muxval(EMI1_SLOT4);
 759                         wriop_set_mdio(dpmac_id, bus);
 760                 break;
 761                 case 5:
 762                         if (slot == EMI_NONE)
 763                                 return;
 764                         if (serdes2_prtcl == 0x47) {
 765                                 wriop_set_phy_address(dpmac_id, 0,
 766                                               riser_phy_addr[dpmac_id - 10]);
 767                                 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
 768                                                                  env_hwconfig))
 769                                         wriop_set_phy_address(dpmac_id, 0,
 770                                                 riser_phy_addr[dpmac_id - 11]);
 771                         } else {
 772                                 wriop_set_phy_address(dpmac_id, 0,
 773                                         riser_phy_addr[dpmac_id - 11]);
 774                         }
 775                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
 776                         bus = mii_dev_for_muxval(EMI1_SLOT5);
 777                         wriop_set_mdio(dpmac_id, bus);
 778                         break;
 779                 case 6:
 780                         /* Slot housing a SGMII riser card? */
 781                         wriop_set_phy_address(dpmac_id, 0,
 782                                               riser_phy_addr[dpmac_id - 13]);
 783                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
 784                         bus = mii_dev_for_muxval(EMI1_SLOT6);
 785                         wriop_set_mdio(dpmac_id, bus);
 786                 break;
 787         }
 788         break;
 789         default:
 790                 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
 791                        __func__, serdes2_prtcl);
 792         break;
 793         }
 794 }
 795
 796 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
 797 {
 798         int lane = 0, slot;
 799         struct mii_dev *bus;
 800         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 801         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 802                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 803                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 804
 805         switch (serdes1_prtcl) {
 806         case 0x33:
 807                 switch (dpmac_id) {
 808                 case 1:
 809                 case 2:
 810                 case 3:
 811                 case 4:
 812                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
 813                 break;
 814                 case 5:
 815                 case 6:
 816                 case 7:
 817                 case 8:
 818                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
 819                 break;
 820                 case 9:
 821                 case 10:
 822                 case 11:
 823                 case 12:
 824                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
 825                 break;
 826                 case 13:
 827                 case 14:
 828                 case 15:
 829                 case 16:
 830                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
 831                 break;
 832         }
 833
 834                 slot = lane_to_slot_fsm1[lane];
 835
 836                 switch (++slot) {
 837                 case 1:
 838                         /* Slot housing a QSGMII riser card? */
 839                         wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
 840                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
 841                         bus = mii_dev_for_muxval(EMI1_SLOT1);
 842                         wriop_set_mdio(dpmac_id, bus);
 843                         break;
 844                 case 3:
 845                         break;
 846                 case 4:
 847                         break;
 848                 case 5:
 849                 break;
 850                 case 6:
 851                         break;
 852         }
 853         break;
 854         default:
 855                 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
 856                        serdes1_prtcl);
 857         break;
 858         }
 859
 860         qsgmii_configure_repeater(dpmac_id);
 861 }
 862
 863 void ls2080a_handle_phy_interface_xsgmii(int i)
 864 {
 865         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 866         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 867                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 868                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 869
 870         switch (serdes1_prtcl) {
 871         case 0x2A:
 872         case 0x4B:
 873         case 0x4C:
 874                 /*
 875                  * XFI does not need a PHY to work, but to avoid U-Boot use
 876                  * default PHY address which is zero to a MAC when it found
 877                  * a MAC has no PHY address, we give a PHY address to XFI
 878                  * MAC, and should not use a real XAUI PHY address, since
 879                  * MDIO can access it successfully, and then MDIO thinks
 880                  * the XAUI card is used for the XFI MAC, which will cause
 881                  * error.
 882                  */
 883                 wriop_set_phy_address(i, 0, i + 4);
 884                 ls2080a_qds_enable_SFP_TX(SFP_TX);
 885
 886                 break;
 887         default:
 888                 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
 889                        serdes1_prtcl);
 890                 break;
 891         }
 892 }
 893 #endif
 894
 895 int board_eth_init(bd_t *bis)
 896 {
 897         int error;
 898 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 899         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 900         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 901                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 902                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 903         int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
 904                                 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
 905                 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
 906
 907         struct memac_mdio_info *memac_mdio0_info;
 908         struct memac_mdio_info *memac_mdio1_info;
 909         unsigned int i;
 910         char *env_hwconfig;
 911
 912         env_hwconfig = env_get("hwconfig");
 913
 914         initialize_dpmac_to_slot();
 915
 916         memac_mdio0_info = (struct memac_mdio_info *)malloc(
 917                                         sizeof(struct memac_mdio_info));
 918         memac_mdio0_info->regs =
 919                 (struct memac_mdio_controller *)
 920                                         CONFIG_SYS_FSL_WRIOP1_MDIO1;
 921         memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
 922
 923         /* Register the real MDIO1 bus */
 924         fm_memac_mdio_init(bis, memac_mdio0_info);
 925
 926         memac_mdio1_info = (struct memac_mdio_info *)malloc(
 927                                         sizeof(struct memac_mdio_info));
 928         memac_mdio1_info->regs =
 929                 (struct memac_mdio_controller *)
 930                                         CONFIG_SYS_FSL_WRIOP1_MDIO2;
 931         memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
 932
 933         /* Register the real MDIO2 bus */
 934         fm_memac_mdio_init(bis, memac_mdio1_info);
 935
 936         /* Register the muxing front-ends to the MDIO buses */
 937         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
 938         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
 939         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
 940         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
 941         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
 942         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
 943
 944         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
 945
 946         for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 947                 switch (wriop_get_enet_if(i)) {
 948                 case PHY_INTERFACE_MODE_QSGMII:
 949                         ls2080a_handle_phy_interface_qsgmii(i);
 950                         break;
 951                 case PHY_INTERFACE_MODE_SGMII:
 952                         ls2080a_handle_phy_interface_sgmii(i);
 953                         break;
 954                 case PHY_INTERFACE_MODE_XGMII:
 955                         ls2080a_handle_phy_interface_xsgmii(i);
 956                         break;
 957                 default:
 958                         break;
 959
 960                 if (i == 16)
 961                         i = NUM_WRIOP_PORTS;
 962                 }
 963         }
 964
 965         error = cpu_eth_init(bis);
 966
 967         if (hwconfig_f("xqsgmii", env_hwconfig)) {
 968                 if (serdes1_prtcl == 0x7)
 969                         sgmii_configure_repeater(1);
 970                 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
 971                     serdes2_prtcl == 0x49)
 972                         sgmii_configure_repeater(2);
 973         }
 974 #endif
 975         error = pci_eth_init(bis);
 976         return error;
 977 }
 978
 979 #if defined(CONFIG_RESET_PHY_R)
 980 void reset_phy(void)
 981 {
 982         mc_env_boot();
 983 }
 984 #endif /* CONFIG_RESET_PHY_R */