board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <env.h>
   7 #include <i2c.h>
   8 #include <malloc.h>
   9 #include <errno.h>
  10 #include <netdev.h>
  11 #include <fsl_ifc.h>
  12 #include <fsl_ddr.h>
  13 #include <fsl_sec.h>
  14 #include <asm/io.h>
  15 #include <fdt_support.h>
  16 #include <linux/libfdt.h>
  17 #include <fsl-mc/fsl_mc.h>
  18 #include <env_internal.h>
  19 #include <asm/arch-fsl-layerscape/soc.h>
  20 #include <asm/arch/ppa.h>
  21 #include <hwconfig.h>
  22 #include <asm/arch/fsl_serdes.h>
  23 #include <asm/arch/soc.h>
  24 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  25
  26 #include "../common/qixis.h"
  27 #include "ls1088a_qixis.h"
  28 #include "../common/vid.h"
  29 #include <fsl_immap.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #ifdef CONFIG_TARGET_LS1088AQDS
  34 #ifdef CONFIG_TFABOOT
  35 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  36         {
  37                 "nor0",
  38                 CONFIG_SYS_NOR0_CSPR_EARLY,
  39                 CONFIG_SYS_NOR0_CSPR_EXT,
  40                 CONFIG_SYS_NOR_AMASK,
  41                 CONFIG_SYS_NOR_CSOR,
  42                 {
  43                         CONFIG_SYS_NOR_FTIM0,
  44                         CONFIG_SYS_NOR_FTIM1,
  45                         CONFIG_SYS_NOR_FTIM2,
  46                         CONFIG_SYS_NOR_FTIM3
  47                 },
  48                 0,
  49                 CONFIG_SYS_NOR0_CSPR,
  50                 0,
  51         },
  52         {
  53                 "nor1",
  54                 CONFIG_SYS_NOR1_CSPR_EARLY,
  55                 CONFIG_SYS_NOR0_CSPR_EXT,
  56                 CONFIG_SYS_NOR_AMASK_EARLY,
  57                 CONFIG_SYS_NOR_CSOR,
  58                 {
  59                         CONFIG_SYS_NOR_FTIM0,
  60                         CONFIG_SYS_NOR_FTIM1,
  61                         CONFIG_SYS_NOR_FTIM2,
  62                         CONFIG_SYS_NOR_FTIM3
  63                 },
  64                 0,
  65                 CONFIG_SYS_NOR1_CSPR,
  66                 CONFIG_SYS_NOR_AMASK,
  67         },
  68         {
  69                 "nand",
  70                 CONFIG_SYS_NAND_CSPR,
  71                 CONFIG_SYS_NAND_CSPR_EXT,
  72                 CONFIG_SYS_NAND_AMASK,
  73                 CONFIG_SYS_NAND_CSOR,
  74                 {
  75                         CONFIG_SYS_NAND_FTIM0,
  76                         CONFIG_SYS_NAND_FTIM1,
  77                         CONFIG_SYS_NAND_FTIM2,
  78                         CONFIG_SYS_NAND_FTIM3
  79                 },
  80         },
  81         {
  82                 "fpga",
  83                 CONFIG_SYS_FPGA_CSPR,
  84                 CONFIG_SYS_FPGA_CSPR_EXT,
  85                 SYS_FPGA_AMASK,
  86                 CONFIG_SYS_FPGA_CSOR,
  87                 {
  88                         SYS_FPGA_CS_FTIM0,
  89                         SYS_FPGA_CS_FTIM1,
  90                         SYS_FPGA_CS_FTIM2,
  91                         SYS_FPGA_CS_FTIM3
  92                 },
  93                 0,
  94                 SYS_FPGA_CSPR_FINAL,
  95                 0,
  96         }
  97 };
  98
  99 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 100         {
 101                 "nand",
 102                 CONFIG_SYS_NAND_CSPR,
 103                 CONFIG_SYS_NAND_CSPR_EXT,
 104                 CONFIG_SYS_NAND_AMASK,
 105                 CONFIG_SYS_NAND_CSOR,
 106                 {
 107                         CONFIG_SYS_NAND_FTIM0,
 108                         CONFIG_SYS_NAND_FTIM1,
 109                         CONFIG_SYS_NAND_FTIM2,
 110                         CONFIG_SYS_NAND_FTIM3
 111                 },
 112         },
 113         {
 114                 "reserved",
 115         },
 116         {
 117                 "fpga",
 118                 CONFIG_SYS_FPGA_CSPR,
 119                 CONFIG_SYS_FPGA_CSPR_EXT,
 120                 SYS_FPGA_AMASK,
 121                 CONFIG_SYS_FPGA_CSOR,
 122                 {
 123                         SYS_FPGA_CS_FTIM0,
 124                         SYS_FPGA_CS_FTIM1,
 125                         SYS_FPGA_CS_FTIM2,
 126                         SYS_FPGA_CS_FTIM3
 127                 },
 128                 0,
 129                 SYS_FPGA_CSPR_FINAL,
 130                 0,
 131         }
 132 };
 133
 134 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 135 {
 136         enum boot_src src = get_boot_src();
 137
 138         if (src == BOOT_SOURCE_QSPI_NOR)
 139                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 140         else
 141                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 142
 143         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 144 }
 145 #endif /* CONFIG_TFABOOT */
 146 #endif /* CONFIG_TARGET_LS1088AQDS */
 147
 148 int board_early_init_f(void)
 149 {
 150 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 151         i2c_early_init_f();
 152 #endif
 153         fsl_lsch3_early_init_f();
 154         return 0;
 155 }
 156
 157 #ifdef CONFIG_FSL_QIXIS
 158 unsigned long long get_qixis_addr(void)
 159 {
 160         unsigned long long addr;
 161
 162         if (gd->flags & GD_FLG_RELOC)
 163                 addr = QIXIS_BASE_PHYS;
 164         else
 165                 addr = QIXIS_BASE_PHYS_EARLY;
 166
 167         /*
 168          * IFC address under 256MB is mapped to 0x30000000, any address above
 169          * is mapped to 0x5_10000000 up to 4GB.
 170          */
 171         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 172
 173         return addr;
 174 }
 175 #endif
 176
 177 #if defined(CONFIG_VID)
 178 int init_func_vid(void)
 179 {
 180         if (adjust_vdd(0) < 0)
 181                 printf("core voltage not adjusted\n");
 182
 183         return 0;
 184 }
 185 #endif
 186
 187 int is_pb_board(void)
 188 {
 189         u8 board_id;
 190
 191         board_id = QIXIS_READ(id);
 192         if (board_id == LS1088ARDB_PB_BOARD)
 193                 return 1;
 194         else
 195                 return 0;
 196 }
 197
 198 int fixup_ls1088ardb_pb_banner(void *fdt)
 199 {
 200         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 201
 202         return 0;
 203 }
 204
 205 #if !defined(CONFIG_SPL_BUILD)
 206 int checkboard(void)
 207 {
 208 #ifdef CONFIG_TFABOOT
 209         enum boot_src src = get_boot_src();
 210 #endif
 211         char buf[64];
 212         u8 sw;
 213         static const char *const freq[] = {"100", "125", "156.25",
 214                                             "100 separate SSCG"};
 215         int clock;
 216
 217 #ifdef CONFIG_TARGET_LS1088AQDS
 218         printf("Board: LS1088A-QDS, ");
 219 #else
 220         if (is_pb_board())
 221                 printf("Board: LS1088ARDB-PB, ");
 222         else
 223                 printf("Board: LS1088A-RDB, ");
 224 #endif
 225
 226         sw = QIXIS_READ(arch);
 227         printf("Board Arch: V%d, ", sw >> 4);
 228
 229 #ifdef CONFIG_TARGET_LS1088AQDS
 230         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 231 #else
 232         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 233 #endif
 234
 235         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 236
 237         sw = QIXIS_READ(brdcfg[0]);
 238         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 239
 240 #ifdef CONFIG_TFABOOT
 241         if (src == BOOT_SOURCE_SD_MMC)
 242                 puts("SD card\n");
 243 #else
 244 #ifdef CONFIG_SD_BOOT
 245         puts("SD card\n");
 246 #endif
 247 #endif /* CONFIG_TFABOOT */
 248         switch (sw) {
 249 #ifdef CONFIG_TARGET_LS1088AQDS
 250         case 0:
 251         case 1:
 252         case 2:
 253         case 3:
 254         case 4:
 255         case 5:
 256         case 6:
 257         case 7:
 258                 printf("vBank: %d\n", sw);
 259                 break;
 260         case 8:
 261                 puts("PromJet\n");
 262                 break;
 263         case 15:
 264                 puts("IFCCard\n");
 265                 break;
 266         case 14:
 267 #else
 268         case 0:
 269 #endif
 270                 puts("QSPI:");
 271                 sw = QIXIS_READ(brdcfg[0]);
 272                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 273                 if (sw == 0 || sw == 4)
 274                         puts("0\n");
 275                 else if (sw == 1)
 276                         puts("1\n");
 277                 else
 278                         puts("EMU\n");
 279                 break;
 280
 281         default:
 282                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 283                 break;
 284         }
 285
 286 #ifdef CONFIG_TARGET_LS1088AQDS
 287         printf("FPGA: v%d (%s), build %d",
 288                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 289                (int)qixis_read_minor());
 290         /* the timestamp string contains "\n" at the end */
 291         printf(" on %s", qixis_read_time(buf));
 292 #else
 293         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 294 #endif
 295
 296         /*
 297          * Display the actual SERDES reference clocks as configured by the
 298          * dip switches on the board.  Note that the SWx registers could
 299          * technically be set to force the reference clocks to match the
 300          * values that the SERDES expects (or vice versa).  For now, however,
 301          * we just display both values and hope the user notices when they
 302          * don't match.
 303          */
 304         puts("SERDES1 Reference : ");
 305         sw = QIXIS_READ(brdcfg[2]);
 306         clock = (sw >> 6) & 3;
 307         printf("Clock1 = %sMHz ", freq[clock]);
 308         clock = (sw >> 4) & 3;
 309         printf("Clock2 = %sMHz", freq[clock]);
 310
 311         puts("\nSERDES2 Reference : ");
 312         clock = (sw >> 2) & 3;
 313         printf("Clock1 = %sMHz ", freq[clock]);
 314         clock = (sw >> 0) & 3;
 315         printf("Clock2 = %sMHz\n", freq[clock]);
 316
 317         return 0;
 318 }
 319 #endif
 320
 321 bool if_board_diff_clk(void)
 322 {
 323 #ifdef CONFIG_TARGET_LS1088AQDS
 324         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 325         return diff_conf & 0x40;
 326 #else
 327         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 328         return diff_conf & 0x80;
 329 #endif
 330 }
 331
 332 unsigned long get_board_sys_clk(void)
 333 {
 334         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 335
 336         switch (sysclk_conf & 0x0f) {
 337         case QIXIS_SYSCLK_83:
 338                 return 83333333;
 339         case QIXIS_SYSCLK_100:
 340                 return 100000000;
 341         case QIXIS_SYSCLK_125:
 342                 return 125000000;
 343         case QIXIS_SYSCLK_133:
 344                 return 133333333;
 345         case QIXIS_SYSCLK_150:
 346                 return 150000000;
 347         case QIXIS_SYSCLK_160:
 348                 return 160000000;
 349         case QIXIS_SYSCLK_166:
 350                 return 166666666;
 351         }
 352
 353         return 66666666;
 354 }
 355
 356 unsigned long get_board_ddr_clk(void)
 357 {
 358         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 359
 360         if (if_board_diff_clk())
 361                 return get_board_sys_clk();
 362         switch ((ddrclk_conf & 0x30) >> 4) {
 363         case QIXIS_DDRCLK_100:
 364                 return 100000000;
 365         case QIXIS_DDRCLK_125:
 366                 return 125000000;
 367         case QIXIS_DDRCLK_133:
 368                 return 133333333;
 369         }
 370
 371         return 66666666;
 372 }
 373
 374 int select_i2c_ch_pca9547(u8 ch)
 375 {
 376         int ret;
 377
 378 #ifndef CONFIG_DM_I2C
 379         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 380 #else
 381         struct udevice *dev;
 382
 383         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
 384         if (!ret)
 385                 ret = dm_i2c_write(dev, 0, &ch, 1);
 386 #endif
 387         if (ret) {
 388                 puts("PCA: failed to select proper channel\n");
 389                 return ret;
 390         }
 391
 392         return 0;
 393 }
 394
 395 #if !defined(CONFIG_SPL_BUILD)
 396 void board_retimer_init(void)
 397 {
 398         u8 reg;
 399
 400         /* Retimer is connected to I2C1_CH5 */
 401         select_i2c_ch_pca9547(I2C_MUX_CH5);
 402
 403         /* Access to Control/Shared register */
 404         reg = 0x0;
 405 #ifndef CONFIG_DM_I2C
 406         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 407 #else
 408         struct udevice *dev;
 409
 410         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 411         dm_i2c_write(dev, 0xff, &reg, 1);
 412 #endif
 413
 414         /* Read device revision and ID */
 415 #ifndef CONFIG_DM_I2C
 416         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 417 #else
 418         dm_i2c_read(dev, 1, &reg, 1);
 419 #endif
 420         debug("Retimer version id = 0x%x\n", reg);
 421
 422         /* Enable Broadcast. All writes target all channel register sets */
 423         reg = 0x0c;
 424 #ifndef CONFIG_DM_I2C
 425         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 426 #else
 427         dm_i2c_write(dev, 0xff, &reg, 1);
 428 #endif
 429
 430         /* Reset Channel Registers */
 431 #ifndef CONFIG_DM_I2C
 432         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 433 #else
 434         dm_i2c_read(dev, 0, &reg, 1);
 435 #endif
 436         reg |= 0x4;
 437 #ifndef CONFIG_DM_I2C
 438         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 439 #else
 440         dm_i2c_write(dev, 0, &reg, 1);
 441 #endif
 442
 443         /* Set data rate as 10.3125 Gbps */
 444         reg = 0x90;
 445 #ifndef CONFIG_DM_I2C
 446         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 447 #else
 448         dm_i2c_write(dev, 0x60, &reg, 1);
 449 #endif
 450         reg = 0xb3;
 451 #ifndef CONFIG_DM_I2C
 452         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 453 #else
 454         dm_i2c_write(dev, 0x61, &reg, 1);
 455 #endif
 456         reg = 0x90;
 457 #ifndef CONFIG_DM_I2C
 458         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 459 #else
 460         dm_i2c_write(dev, 0x62, &reg, 1);
 461 #endif
 462         reg = 0xb3;
 463 #ifndef CONFIG_DM_I2C
 464         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 465 #else
 466         dm_i2c_write(dev, 0x63, &reg, 1);
 467 #endif
 468         reg = 0xcd;
 469 #ifndef CONFIG_DM_I2C
 470         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 471 #else
 472         dm_i2c_write(dev, 0x64, &reg, 1);
 473 #endif
 474
 475         /* Select VCO Divider to full rate (000) */
 476 #ifndef CONFIG_DM_I2C
 477         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 478 #else
 479         dm_i2c_read(dev, 0x2F, &reg, 1);
 480 #endif
 481         reg &= 0x0f;
 482         reg |= 0x70;
 483 #ifndef CONFIG_DM_I2C
 484         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 485 #else
 486         dm_i2c_write(dev, 0x2F, &reg, 1);
 487 #endif
 488
 489 #ifdef  CONFIG_TARGET_LS1088AQDS
 490         /* Retimer is connected to I2C1_CH5 */
 491         select_i2c_ch_pca9547(I2C_MUX_CH5);
 492
 493         /* Access to Control/Shared register */
 494         reg = 0x0;
 495 #ifndef CONFIG_DM_I2C
 496         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 497 #else
 498         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 499         dm_i2c_write(dev, 0xff, &reg, 1);
 500 #endif
 501
 502         /* Read device revision and ID */
 503 #ifndef CONFIG_DM_I2C
 504         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 505 #else
 506         dm_i2c_read(dev, 1, &reg, 1);
 507 #endif
 508         debug("Retimer version id = 0x%x\n", reg);
 509
 510         /* Enable Broadcast. All writes target all channel register sets */
 511         reg = 0x0c;
 512 #ifndef CONFIG_DM_I2C
 513         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 514 #else
 515         dm_i2c_write(dev, 0xff, &reg, 1);
 516 #endif
 517
 518         /* Reset Channel Registers */
 519 #ifndef CONFIG_DM_I2C
 520         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 521 #else
 522         dm_i2c_read(dev, 0, &reg, 1);
 523 #endif
 524         reg |= 0x4;
 525 #ifndef CONFIG_DM_I2C
 526         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 527 #else
 528         dm_i2c_write(dev, 0, &reg, 1);
 529 #endif
 530
 531         /* Set data rate as 10.3125 Gbps */
 532         reg = 0x90;
 533 #ifndef CONFIG_DM_I2C
 534         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 535 #else
 536         dm_i2c_write(dev, 0x60, &reg, 1);
 537 #endif
 538         reg = 0xb3;
 539 #ifndef CONFIG_DM_I2C
 540         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 541 #else
 542         dm_i2c_write(dev, 0x61, &reg, 1);
 543 #endif
 544         reg = 0x90;
 545 #ifndef CONFIG_DM_I2C
 546         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 547 #else
 548         dm_i2c_write(dev, 0x62, &reg, 1);
 549 #endif
 550         reg = 0xb3;
 551 #ifndef CONFIG_DM_I2C
 552         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 553 #else
 554         dm_i2c_write(dev, 0x63, &reg, 1);
 555 #endif
 556         reg = 0xcd;
 557 #ifndef CONFIG_DM_I2C
 558         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 559 #else
 560         dm_i2c_write(dev, 0x64, &reg, 1);
 561 #endif
 562
 563         /* Select VCO Divider to full rate (000) */
 564 #ifndef CONFIG_DM_I2C
 565         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 566 #else
 567         dm_i2c_read(dev, 0x2F, &reg, 1);
 568 #endif
 569         reg &= 0x0f;
 570         reg |= 0x70;
 571 #ifndef CONFIG_DM_I2C
 572         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 573 #else
 574         dm_i2c_write(dev, 0x2F, &reg, 1);
 575 #endif
 576
 577 #endif
 578         /*return the default channel*/
 579         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 580 }
 581
 582 #ifdef CONFIG_MISC_INIT_R
 583 int misc_init_r(void)
 584 {
 585 #ifdef CONFIG_TARGET_LS1088ARDB
 586         u8 brdcfg5;
 587
 588         if (hwconfig("esdhc-force-sd")) {
 589                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 590                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 591                 brdcfg5 |= BRDCFG5_FORCE_SD;
 592                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 593         }
 594 #endif
 595
 596 #ifdef CONFIG_TARGET_LS1088AQDS
 597          u8 brdcfg4, brdcfg5;
 598
 599         if (hwconfig("dspi-on-board")) {
 600                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 601                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 602                 brdcfg4 |= BRDCFG4_SPI;
 603                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 604
 605                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 606                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 607                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 608                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 609         } else if (hwconfig("dspi-off-board")) {
 610                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 611                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 612                 brdcfg4 |= BRDCFG4_SPI;
 613                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 614
 615                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 616                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 617                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 618                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 619         }
 620 #endif
 621         return 0;
 622 }
 623 #endif
 624 #endif
 625
 626 int i2c_multiplexer_select_vid_channel(u8 channel)
 627 {
 628         return select_i2c_ch_pca9547(channel);
 629 }
 630
 631 #ifdef CONFIG_TARGET_LS1088AQDS
 632 /* read the current value(SVDD) of the LTM Regulator Voltage */
 633 int get_serdes_volt(void)
 634 {
 635         int  ret, vcode = 0;
 636         u8 chan = PWM_CHANNEL0;
 637
 638         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 639 #ifndef CONFIG_DM_I2C
 640         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 641                         PMBUS_CMD_PAGE, 1, &chan, 1);
 642 #else
 643         struct udevice *dev;
 644
 645         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 646         if (!ret)
 647                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 648                                    &chan, 1);
 649 #endif
 650
 651         if (ret) {
 652                 printf("VID: failed to select VDD Page 0\n");
 653                 return ret;
 654         }
 655
 656         /* Read the output voltage using PMBus command READ_VOUT */
 657 #ifndef CONFIG_DM_I2C
 658         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 659                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 660 #else
 661         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 662 #endif
 663         if (ret) {
 664                 printf("VID: failed to read the volatge\n");
 665                 return ret;
 666         }
 667
 668         return vcode;
 669 }
 670
 671 int set_serdes_volt(int svdd)
 672 {
 673         int ret, vdd_last;
 674         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 675                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 676
 677         /* Write the desired voltage code to the SVDD regulator */
 678 #ifndef CONFIG_DM_I2C
 679         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 680                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 681 #else
 682         struct udevice *dev;
 683
 684         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 685         if (!ret)
 686                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 687                                    (void *)&buff, 5);
 688 #endif
 689         if (ret) {
 690                 printf("VID: I2C failed to write to the volatge regulator\n");
 691                 return -1;
 692         }
 693
 694         /* Wait for the volatge to get to the desired value */
 695         do {
 696                 vdd_last = get_serdes_volt();
 697                 if (vdd_last < 0) {
 698                         printf("VID: Couldn't read sensor abort VID adjust\n");
 699                         return -1;
 700                 }
 701         } while (vdd_last != svdd);
 702
 703         return 1;
 704 }
 705 #else
 706 int get_serdes_volt(void)
 707 {
 708         return 0;
 709 }
 710
 711 int set_serdes_volt(int svdd)
 712 {
 713         int ret;
 714         u8 brdcfg4;
 715
 716         printf("SVDD changing of RDB\n");
 717
 718         /* Read the BRDCFG54 via CLPD */
 719 #ifndef CONFIG_DM_I2C
 720         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 721                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 722 #else
 723         struct udevice *dev;
 724
 725         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 726         if (!ret)
 727                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 728                                   (void *)&brdcfg4, 1);
 729 #endif
 730
 731         if (ret) {
 732                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 733                 return -1;
 734         }
 735
 736         brdcfg4 = brdcfg4 | 0x08;
 737
 738         /* Write to the BRDCFG4 */
 739 #ifndef CONFIG_DM_I2C
 740         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 741                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 742 #else
 743         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 744                            (void *)&brdcfg4, 1);
 745 #endif
 746
 747         if (ret) {
 748                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 749                 return -1;
 750         }
 751
 752         /* Wait for the volatge to get to the desired value */
 753         udelay(10000);
 754
 755         return 1;
 756 }
 757 #endif
 758
 759 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 760 int board_adjust_vdd(int vdd)
 761 {
 762         int ret = 0;
 763
 764         debug("%s: vdd = %d\n", __func__, vdd);
 765
 766         /* Special settings to be performed when voltage is 900mV */
 767         if (vdd == 900) {
 768                 ret = setup_serdes_volt(vdd);
 769                 if (ret < 0) {
 770                         ret = -1;
 771                         goto exit;
 772                 }
 773         }
 774 exit:
 775         return ret;
 776 }
 777
 778 #if !defined(CONFIG_SPL_BUILD)
 779 int board_init(void)
 780 {
 781         init_final_memctl_regs();
 782 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 783         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 784 #endif
 785
 786         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 787         board_retimer_init();
 788
 789 #ifdef CONFIG_ENV_IS_NOWHERE
 790         gd->env_addr = (ulong)&default_environment[0];
 791 #endif
 792
 793 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 794         /* invert AQR105 IRQ pins polarity */
 795         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 796 #endif
 797
 798 #ifdef CONFIG_FSL_CAAM
 799         sec_init();
 800 #endif
 801 #ifdef CONFIG_FSL_LS_PPA
 802         ppa_init();
 803 #endif
 804         return 0;
 805 }
 806
 807 void detail_board_ddr_info(void)
 808 {
 809         puts("\nDDR    ");
 810         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 811         print_ddr_info(0);
 812 }
 813
 814 #if defined(CONFIG_ARCH_MISC_INIT)
 815 int arch_misc_init(void)
 816 {
 817         return 0;
 818 }
 819 #endif
 820
 821 #ifdef CONFIG_FSL_MC_ENET
 822 void board_quiesce_devices(void)
 823 {
 824         fsl_mc_ldpaa_exit(gd->bd);
 825 }
 826
 827 void fdt_fixup_board_enet(void *fdt)
 828 {
 829         int offset;
 830
 831         offset = fdt_path_offset(fdt, "/fsl-mc");
 832
 833         if (offset < 0)
 834                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 835
 836         if (offset < 0) {
 837                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 838                        __func__, offset);
 839                 return;
 840         }
 841
 842         if (get_mc_boot_status() == 0 &&
 843             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 844                 fdt_status_okay(fdt, offset);
 845         else
 846                 fdt_status_fail(fdt, offset);
 847 }
 848 #endif
 849
 850 #ifdef CONFIG_OF_BOARD_SETUP
 851 void fsl_fdt_fixup_flash(void *fdt)
 852 {
 853         int offset;
 854 #ifdef CONFIG_TFABOOT
 855         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 856         u32 val;
 857 #endif
 858
 859 /*
 860  * IFC-NOR and QSPI are muxed on SoC.
 861  * So disable IFC node in dts if QSPI is enabled or
 862  * disable QSPI node in dts in case QSPI is not enabled.
 863  */
 864
 865 #ifdef CONFIG_TFABOOT
 866         enum boot_src src = get_boot_src();
 867         bool disable_ifc = false;
 868
 869         switch (src) {
 870         case BOOT_SOURCE_IFC_NOR:
 871                 disable_ifc = false;
 872                 break;
 873         case BOOT_SOURCE_QSPI_NOR:
 874                 disable_ifc = true;
 875                 break;
 876         default:
 877                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 878                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 879                         disable_ifc = true;
 880                 break;
 881         }
 882
 883         if (disable_ifc) {
 884                 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 885
 886                 if (offset < 0)
 887                         offset = fdt_path_offset(fdt, "/ifc/nor");
 888         } else {
 889                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 890
 891                 if (offset < 0)
 892                         offset = fdt_path_offset(fdt, "/quadspi");
 893         }
 894
 895 #else
 896 #ifdef CONFIG_FSL_QSPI
 897         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 898
 899         if (offset < 0)
 900                 offset = fdt_path_offset(fdt, "/ifc/nor");
 901 #else
 902         offset = fdt_path_offset(fdt, "/soc/quadspi");
 903
 904         if (offset < 0)
 905                 offset = fdt_path_offset(fdt, "/quadspi");
 906 #endif
 907 #endif
 908         if (offset < 0)
 909                 return;
 910
 911         fdt_status_disabled(fdt, offset);
 912 }
 913
 914 int ft_board_setup(void *blob, bd_t *bd)
 915 {
 916         int i;
 917         u16 mc_memory_bank = 0;
 918
 919         u64 *base;
 920         u64 *size;
 921         u64 mc_memory_base = 0;
 922         u64 mc_memory_size = 0;
 923         u16 total_memory_banks;
 924
 925         ft_cpu_setup(blob, bd);
 926
 927         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 928
 929         if (mc_memory_base != 0)
 930                 mc_memory_bank++;
 931
 932         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 933
 934         base = calloc(total_memory_banks, sizeof(u64));
 935         size = calloc(total_memory_banks, sizeof(u64));
 936
 937         /* fixup DT for the two GPP DDR banks */
 938         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 939                 base[i] = gd->bd->bi_dram[i].start;
 940                 size[i] = gd->bd->bi_dram[i].size;
 941         }
 942
 943 #ifdef CONFIG_RESV_RAM
 944         /* reduce size if reserved memory is within this bank */
 945         if (gd->arch.resv_ram >= base[0] &&
 946             gd->arch.resv_ram < base[0] + size[0])
 947                 size[0] = gd->arch.resv_ram - base[0];
 948         else if (gd->arch.resv_ram >= base[1] &&
 949                  gd->arch.resv_ram < base[1] + size[1])
 950                 size[1] = gd->arch.resv_ram - base[1];
 951 #endif
 952
 953         if (mc_memory_base != 0) {
 954                 for (i = 0; i <= total_memory_banks; i++) {
 955                         if (base[i] == 0 && size[i] == 0) {
 956                                 base[i] = mc_memory_base;
 957                                 size[i] = mc_memory_size;
 958                                 break;
 959                         }
 960                 }
 961         }
 962
 963         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 964
 965         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 966
 967         fsl_fdt_fixup_flash(blob);
 968
 969 #ifdef CONFIG_FSL_MC_ENET
 970         fdt_fixup_board_enet(blob);
 971 #endif
 972
 973         fdt_fixup_icid(blob);
 974
 975         if (is_pb_board())
 976                 fixup_ls1088ardb_pb_banner(blob);
 977
 978         return 0;
 979 }
 980 #endif
 981 #endif /* defined(CONFIG_SPL_BUILD) */
 982
 983 #ifdef CONFIG_TFABOOT
 984 #ifdef CONFIG_MTD_NOR_FLASH
 985 int is_flash_available(void)
 986 {
 987         char *env_hwconfig = env_get("hwconfig");
 988         enum boot_src src = get_boot_src();
 989         int is_nor_flash_available = 1;
 990
 991         switch (src) {
 992         case BOOT_SOURCE_IFC_NOR:
 993                 is_nor_flash_available = 1;
 994                 break;
 995         case BOOT_SOURCE_QSPI_NOR:
 996                 is_nor_flash_available = 0;
 997                 break;
 998         /*
 999          * In Case of SD boot,if qspi is defined in env_hwconfig
1000          * disable nor flash probe.
1001          */
1002         default:
1003                 if (hwconfig_f("qspi", env_hwconfig))
1004                         is_nor_flash_available = 0;
1005                 break;
1006         }
1007         return is_nor_flash_available;
1008 }
1009 #endif
1010
1011 void *env_sf_get_env_addr(void)
1012 {
1013         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1014 }
1015 #endif