board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <env.h>
   7 #include <i2c.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ifc.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/io.h>
  17 #include <fdt_support.h>
  18 #include <linux/libfdt.h>
  19 #include <fsl-mc/fsl_mc.h>
  20 #include <env_internal.h>
  21 #include <asm/arch-fsl-layerscape/soc.h>
  22 #include <asm/arch/ppa.h>
  23 #include <hwconfig.h>
  24 #include <asm/arch/fsl_serdes.h>
  25 #include <asm/arch/soc.h>
  26 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  27
  28 #include "../common/qixis.h"
  29 #include "ls1088a_qixis.h"
  30 #include "../common/vid.h"
  31 #include <fsl_immap.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #ifdef CONFIG_TARGET_LS1088AQDS
  36 #ifdef CONFIG_TFABOOT
  37 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  38         {
  39                 "nor0",
  40                 CONFIG_SYS_NOR0_CSPR_EARLY,
  41                 CONFIG_SYS_NOR0_CSPR_EXT,
  42                 CONFIG_SYS_NOR_AMASK,
  43                 CONFIG_SYS_NOR_CSOR,
  44                 {
  45                         CONFIG_SYS_NOR_FTIM0,
  46                         CONFIG_SYS_NOR_FTIM1,
  47                         CONFIG_SYS_NOR_FTIM2,
  48                         CONFIG_SYS_NOR_FTIM3
  49                 },
  50                 0,
  51                 CONFIG_SYS_NOR0_CSPR,
  52                 0,
  53         },
  54         {
  55                 "nor1",
  56                 CONFIG_SYS_NOR1_CSPR_EARLY,
  57                 CONFIG_SYS_NOR0_CSPR_EXT,
  58                 CONFIG_SYS_NOR_AMASK_EARLY,
  59                 CONFIG_SYS_NOR_CSOR,
  60                 {
  61                         CONFIG_SYS_NOR_FTIM0,
  62                         CONFIG_SYS_NOR_FTIM1,
  63                         CONFIG_SYS_NOR_FTIM2,
  64                         CONFIG_SYS_NOR_FTIM3
  65                 },
  66                 0,
  67                 CONFIG_SYS_NOR1_CSPR,
  68                 CONFIG_SYS_NOR_AMASK,
  69         },
  70         {
  71                 "nand",
  72                 CONFIG_SYS_NAND_CSPR,
  73                 CONFIG_SYS_NAND_CSPR_EXT,
  74                 CONFIG_SYS_NAND_AMASK,
  75                 CONFIG_SYS_NAND_CSOR,
  76                 {
  77                         CONFIG_SYS_NAND_FTIM0,
  78                         CONFIG_SYS_NAND_FTIM1,
  79                         CONFIG_SYS_NAND_FTIM2,
  80                         CONFIG_SYS_NAND_FTIM3
  81                 },
  82         },
  83         {
  84                 "fpga",
  85                 CONFIG_SYS_FPGA_CSPR,
  86                 CONFIG_SYS_FPGA_CSPR_EXT,
  87                 SYS_FPGA_AMASK,
  88                 CONFIG_SYS_FPGA_CSOR,
  89                 {
  90                         SYS_FPGA_CS_FTIM0,
  91                         SYS_FPGA_CS_FTIM1,
  92                         SYS_FPGA_CS_FTIM2,
  93                         SYS_FPGA_CS_FTIM3
  94                 },
  95                 0,
  96                 SYS_FPGA_CSPR_FINAL,
  97                 0,
  98         }
  99 };
 100
 101 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 102         {
 103                 "nand",
 104                 CONFIG_SYS_NAND_CSPR,
 105                 CONFIG_SYS_NAND_CSPR_EXT,
 106                 CONFIG_SYS_NAND_AMASK,
 107                 CONFIG_SYS_NAND_CSOR,
 108                 {
 109                         CONFIG_SYS_NAND_FTIM0,
 110                         CONFIG_SYS_NAND_FTIM1,
 111                         CONFIG_SYS_NAND_FTIM2,
 112                         CONFIG_SYS_NAND_FTIM3
 113                 },
 114         },
 115         {
 116                 "reserved",
 117         },
 118         {
 119                 "fpga",
 120                 CONFIG_SYS_FPGA_CSPR,
 121                 CONFIG_SYS_FPGA_CSPR_EXT,
 122                 SYS_FPGA_AMASK,
 123                 CONFIG_SYS_FPGA_CSOR,
 124                 {
 125                         SYS_FPGA_CS_FTIM0,
 126                         SYS_FPGA_CS_FTIM1,
 127                         SYS_FPGA_CS_FTIM2,
 128                         SYS_FPGA_CS_FTIM3
 129                 },
 130                 0,
 131                 SYS_FPGA_CSPR_FINAL,
 132                 0,
 133         }
 134 };
 135
 136 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 137 {
 138         enum boot_src src = get_boot_src();
 139
 140         if (src == BOOT_SOURCE_QSPI_NOR)
 141                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 142         else
 143                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 144
 145         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 146 }
 147 #endif /* CONFIG_TFABOOT */
 148 #endif /* CONFIG_TARGET_LS1088AQDS */
 149
 150 int board_early_init_f(void)
 151 {
 152 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 153         i2c_early_init_f();
 154 #endif
 155         fsl_lsch3_early_init_f();
 156         return 0;
 157 }
 158
 159 #ifdef CONFIG_FSL_QIXIS
 160 unsigned long long get_qixis_addr(void)
 161 {
 162         unsigned long long addr;
 163
 164         if (gd->flags & GD_FLG_RELOC)
 165                 addr = QIXIS_BASE_PHYS;
 166         else
 167                 addr = QIXIS_BASE_PHYS_EARLY;
 168
 169         /*
 170          * IFC address under 256MB is mapped to 0x30000000, any address above
 171          * is mapped to 0x5_10000000 up to 4GB.
 172          */
 173         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 174
 175         return addr;
 176 }
 177 #endif
 178
 179 #if defined(CONFIG_VID)
 180 int init_func_vid(void)
 181 {
 182         if (adjust_vdd(0) < 0)
 183                 printf("core voltage not adjusted\n");
 184
 185         return 0;
 186 }
 187 #endif
 188
 189 int is_pb_board(void)
 190 {
 191         u8 board_id;
 192
 193         board_id = QIXIS_READ(id);
 194         if (board_id == LS1088ARDB_PB_BOARD)
 195                 return 1;
 196         else
 197                 return 0;
 198 }
 199
 200 int fixup_ls1088ardb_pb_banner(void *fdt)
 201 {
 202         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 203
 204         return 0;
 205 }
 206
 207 #if !defined(CONFIG_SPL_BUILD)
 208 int checkboard(void)
 209 {
 210 #ifdef CONFIG_TFABOOT
 211         enum boot_src src = get_boot_src();
 212 #endif
 213         char buf[64];
 214         u8 sw;
 215         static const char *const freq[] = {"100", "125", "156.25",
 216                                             "100 separate SSCG"};
 217         int clock;
 218
 219 #ifdef CONFIG_TARGET_LS1088AQDS
 220         printf("Board: LS1088A-QDS, ");
 221 #else
 222         if (is_pb_board())
 223                 printf("Board: LS1088ARDB-PB, ");
 224         else
 225                 printf("Board: LS1088A-RDB, ");
 226 #endif
 227
 228         sw = QIXIS_READ(arch);
 229         printf("Board Arch: V%d, ", sw >> 4);
 230
 231 #ifdef CONFIG_TARGET_LS1088AQDS
 232         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 233 #else
 234         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 235 #endif
 236
 237         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 238
 239         sw = QIXIS_READ(brdcfg[0]);
 240         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 241
 242 #ifdef CONFIG_TFABOOT
 243         if (src == BOOT_SOURCE_SD_MMC)
 244                 puts("SD card\n");
 245 #else
 246 #ifdef CONFIG_SD_BOOT
 247         puts("SD card\n");
 248 #endif
 249 #endif /* CONFIG_TFABOOT */
 250         switch (sw) {
 251 #ifdef CONFIG_TARGET_LS1088AQDS
 252         case 0:
 253         case 1:
 254         case 2:
 255         case 3:
 256         case 4:
 257         case 5:
 258         case 6:
 259         case 7:
 260                 printf("vBank: %d\n", sw);
 261                 break;
 262         case 8:
 263                 puts("PromJet\n");
 264                 break;
 265         case 15:
 266                 puts("IFCCard\n");
 267                 break;
 268         case 14:
 269 #else
 270         case 0:
 271 #endif
 272                 puts("QSPI:");
 273                 sw = QIXIS_READ(brdcfg[0]);
 274                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 275                 if (sw == 0 || sw == 4)
 276                         puts("0\n");
 277                 else if (sw == 1)
 278                         puts("1\n");
 279                 else
 280                         puts("EMU\n");
 281                 break;
 282
 283         default:
 284                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 285                 break;
 286         }
 287
 288 #ifdef CONFIG_TARGET_LS1088AQDS
 289         printf("FPGA: v%d (%s), build %d",
 290                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 291                (int)qixis_read_minor());
 292         /* the timestamp string contains "\n" at the end */
 293         printf(" on %s", qixis_read_time(buf));
 294 #else
 295         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 296 #endif
 297
 298         /*
 299          * Display the actual SERDES reference clocks as configured by the
 300          * dip switches on the board.  Note that the SWx registers could
 301          * technically be set to force the reference clocks to match the
 302          * values that the SERDES expects (or vice versa).  For now, however,
 303          * we just display both values and hope the user notices when they
 304          * don't match.
 305          */
 306         puts("SERDES1 Reference : ");
 307         sw = QIXIS_READ(brdcfg[2]);
 308         clock = (sw >> 6) & 3;
 309         printf("Clock1 = %sMHz ", freq[clock]);
 310         clock = (sw >> 4) & 3;
 311         printf("Clock2 = %sMHz", freq[clock]);
 312
 313         puts("\nSERDES2 Reference : ");
 314         clock = (sw >> 2) & 3;
 315         printf("Clock1 = %sMHz ", freq[clock]);
 316         clock = (sw >> 0) & 3;
 317         printf("Clock2 = %sMHz\n", freq[clock]);
 318
 319         return 0;
 320 }
 321 #endif
 322
 323 bool if_board_diff_clk(void)
 324 {
 325 #ifdef CONFIG_TARGET_LS1088AQDS
 326         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 327         return diff_conf & 0x40;
 328 #else
 329         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 330         return diff_conf & 0x80;
 331 #endif
 332 }
 333
 334 unsigned long get_board_sys_clk(void)
 335 {
 336         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 337
 338         switch (sysclk_conf & 0x0f) {
 339         case QIXIS_SYSCLK_83:
 340                 return 83333333;
 341         case QIXIS_SYSCLK_100:
 342                 return 100000000;
 343         case QIXIS_SYSCLK_125:
 344                 return 125000000;
 345         case QIXIS_SYSCLK_133:
 346                 return 133333333;
 347         case QIXIS_SYSCLK_150:
 348                 return 150000000;
 349         case QIXIS_SYSCLK_160:
 350                 return 160000000;
 351         case QIXIS_SYSCLK_166:
 352                 return 166666666;
 353         }
 354
 355         return 66666666;
 356 }
 357
 358 unsigned long get_board_ddr_clk(void)
 359 {
 360         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 361
 362         if (if_board_diff_clk())
 363                 return get_board_sys_clk();
 364         switch ((ddrclk_conf & 0x30) >> 4) {
 365         case QIXIS_DDRCLK_100:
 366                 return 100000000;
 367         case QIXIS_DDRCLK_125:
 368                 return 125000000;
 369         case QIXIS_DDRCLK_133:
 370                 return 133333333;
 371         }
 372
 373         return 66666666;
 374 }
 375
 376 int select_i2c_ch_pca9547(u8 ch)
 377 {
 378         int ret;
 379
 380 #ifndef CONFIG_DM_I2C
 381         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 382 #else
 383         struct udevice *dev;
 384
 385         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
 386         if (!ret)
 387                 ret = dm_i2c_write(dev, 0, &ch, 1);
 388 #endif
 389         if (ret) {
 390                 puts("PCA: failed to select proper channel\n");
 391                 return ret;
 392         }
 393
 394         return 0;
 395 }
 396
 397 #if !defined(CONFIG_SPL_BUILD)
 398 void board_retimer_init(void)
 399 {
 400         u8 reg;
 401
 402         /* Retimer is connected to I2C1_CH5 */
 403         select_i2c_ch_pca9547(I2C_MUX_CH5);
 404
 405         /* Access to Control/Shared register */
 406         reg = 0x0;
 407 #ifndef CONFIG_DM_I2C
 408         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 409 #else
 410         struct udevice *dev;
 411
 412         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 413         dm_i2c_write(dev, 0xff, &reg, 1);
 414 #endif
 415
 416         /* Read device revision and ID */
 417 #ifndef CONFIG_DM_I2C
 418         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 419 #else
 420         dm_i2c_read(dev, 1, &reg, 1);
 421 #endif
 422         debug("Retimer version id = 0x%x\n", reg);
 423
 424         /* Enable Broadcast. All writes target all channel register sets */
 425         reg = 0x0c;
 426 #ifndef CONFIG_DM_I2C
 427         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 428 #else
 429         dm_i2c_write(dev, 0xff, &reg, 1);
 430 #endif
 431
 432         /* Reset Channel Registers */
 433 #ifndef CONFIG_DM_I2C
 434         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 435 #else
 436         dm_i2c_read(dev, 0, &reg, 1);
 437 #endif
 438         reg |= 0x4;
 439 #ifndef CONFIG_DM_I2C
 440         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 441 #else
 442         dm_i2c_write(dev, 0, &reg, 1);
 443 #endif
 444
 445         /* Set data rate as 10.3125 Gbps */
 446         reg = 0x90;
 447 #ifndef CONFIG_DM_I2C
 448         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 449 #else
 450         dm_i2c_write(dev, 0x60, &reg, 1);
 451 #endif
 452         reg = 0xb3;
 453 #ifndef CONFIG_DM_I2C
 454         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 455 #else
 456         dm_i2c_write(dev, 0x61, &reg, 1);
 457 #endif
 458         reg = 0x90;
 459 #ifndef CONFIG_DM_I2C
 460         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 461 #else
 462         dm_i2c_write(dev, 0x62, &reg, 1);
 463 #endif
 464         reg = 0xb3;
 465 #ifndef CONFIG_DM_I2C
 466         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 467 #else
 468         dm_i2c_write(dev, 0x63, &reg, 1);
 469 #endif
 470         reg = 0xcd;
 471 #ifndef CONFIG_DM_I2C
 472         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 473 #else
 474         dm_i2c_write(dev, 0x64, &reg, 1);
 475 #endif
 476
 477         /* Select VCO Divider to full rate (000) */
 478 #ifndef CONFIG_DM_I2C
 479         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 480 #else
 481         dm_i2c_read(dev, 0x2F, &reg, 1);
 482 #endif
 483         reg &= 0x0f;
 484         reg |= 0x70;
 485 #ifndef CONFIG_DM_I2C
 486         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 487 #else
 488         dm_i2c_write(dev, 0x2F, &reg, 1);
 489 #endif
 490
 491 #ifdef  CONFIG_TARGET_LS1088AQDS
 492         /* Retimer is connected to I2C1_CH5 */
 493         select_i2c_ch_pca9547(I2C_MUX_CH5);
 494
 495         /* Access to Control/Shared register */
 496         reg = 0x0;
 497 #ifndef CONFIG_DM_I2C
 498         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 499 #else
 500         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 501         dm_i2c_write(dev, 0xff, &reg, 1);
 502 #endif
 503
 504         /* Read device revision and ID */
 505 #ifndef CONFIG_DM_I2C
 506         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 507 #else
 508         dm_i2c_read(dev, 1, &reg, 1);
 509 #endif
 510         debug("Retimer version id = 0x%x\n", reg);
 511
 512         /* Enable Broadcast. All writes target all channel register sets */
 513         reg = 0x0c;
 514 #ifndef CONFIG_DM_I2C
 515         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 516 #else
 517         dm_i2c_write(dev, 0xff, &reg, 1);
 518 #endif
 519
 520         /* Reset Channel Registers */
 521 #ifndef CONFIG_DM_I2C
 522         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 523 #else
 524         dm_i2c_read(dev, 0, &reg, 1);
 525 #endif
 526         reg |= 0x4;
 527 #ifndef CONFIG_DM_I2C
 528         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 529 #else
 530         dm_i2c_write(dev, 0, &reg, 1);
 531 #endif
 532
 533         /* Set data rate as 10.3125 Gbps */
 534         reg = 0x90;
 535 #ifndef CONFIG_DM_I2C
 536         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 537 #else
 538         dm_i2c_write(dev, 0x60, &reg, 1);
 539 #endif
 540         reg = 0xb3;
 541 #ifndef CONFIG_DM_I2C
 542         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 543 #else
 544         dm_i2c_write(dev, 0x61, &reg, 1);
 545 #endif
 546         reg = 0x90;
 547 #ifndef CONFIG_DM_I2C
 548         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 549 #else
 550         dm_i2c_write(dev, 0x62, &reg, 1);
 551 #endif
 552         reg = 0xb3;
 553 #ifndef CONFIG_DM_I2C
 554         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 555 #else
 556         dm_i2c_write(dev, 0x63, &reg, 1);
 557 #endif
 558         reg = 0xcd;
 559 #ifndef CONFIG_DM_I2C
 560         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 561 #else
 562         dm_i2c_write(dev, 0x64, &reg, 1);
 563 #endif
 564
 565         /* Select VCO Divider to full rate (000) */
 566 #ifndef CONFIG_DM_I2C
 567         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 568 #else
 569         dm_i2c_read(dev, 0x2F, &reg, 1);
 570 #endif
 571         reg &= 0x0f;
 572         reg |= 0x70;
 573 #ifndef CONFIG_DM_I2C
 574         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 575 #else
 576         dm_i2c_write(dev, 0x2F, &reg, 1);
 577 #endif
 578
 579 #endif
 580         /*return the default channel*/
 581         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 582 }
 583
 584 #ifdef CONFIG_MISC_INIT_R
 585 int misc_init_r(void)
 586 {
 587 #ifdef CONFIG_TARGET_LS1088ARDB
 588         u8 brdcfg5;
 589
 590         if (hwconfig("esdhc-force-sd")) {
 591                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 592                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 593                 brdcfg5 |= BRDCFG5_FORCE_SD;
 594                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 595         }
 596 #endif
 597
 598 #ifdef CONFIG_TARGET_LS1088AQDS
 599          u8 brdcfg4, brdcfg5;
 600
 601         if (hwconfig("dspi-on-board")) {
 602                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 603                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 604                 brdcfg4 |= BRDCFG4_SPI;
 605                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 606
 607                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 608                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 609                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 610                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 611         } else if (hwconfig("dspi-off-board")) {
 612                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 613                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 614                 brdcfg4 |= BRDCFG4_SPI;
 615                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 616
 617                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 618                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 619                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 620                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 621         }
 622 #endif
 623         return 0;
 624 }
 625 #endif
 626 #endif
 627
 628 int i2c_multiplexer_select_vid_channel(u8 channel)
 629 {
 630         return select_i2c_ch_pca9547(channel);
 631 }
 632
 633 #ifdef CONFIG_TARGET_LS1088AQDS
 634 /* read the current value(SVDD) of the LTM Regulator Voltage */
 635 int get_serdes_volt(void)
 636 {
 637         int  ret, vcode = 0;
 638         u8 chan = PWM_CHANNEL0;
 639
 640         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 641 #ifndef CONFIG_DM_I2C
 642         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 643                         PMBUS_CMD_PAGE, 1, &chan, 1);
 644 #else
 645         struct udevice *dev;
 646
 647         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 648         if (!ret)
 649                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 650                                    &chan, 1);
 651 #endif
 652
 653         if (ret) {
 654                 printf("VID: failed to select VDD Page 0\n");
 655                 return ret;
 656         }
 657
 658         /* Read the output voltage using PMBus command READ_VOUT */
 659 #ifndef CONFIG_DM_I2C
 660         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 661                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 662 #else
 663         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 664 #endif
 665         if (ret) {
 666                 printf("VID: failed to read the volatge\n");
 667                 return ret;
 668         }
 669
 670         return vcode;
 671 }
 672
 673 int set_serdes_volt(int svdd)
 674 {
 675         int ret, vdd_last;
 676         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 677                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 678
 679         /* Write the desired voltage code to the SVDD regulator */
 680 #ifndef CONFIG_DM_I2C
 681         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 682                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 683 #else
 684         struct udevice *dev;
 685
 686         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 687         if (!ret)
 688                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 689                                    (void *)&buff, 5);
 690 #endif
 691         if (ret) {
 692                 printf("VID: I2C failed to write to the volatge regulator\n");
 693                 return -1;
 694         }
 695
 696         /* Wait for the volatge to get to the desired value */
 697         do {
 698                 vdd_last = get_serdes_volt();
 699                 if (vdd_last < 0) {
 700                         printf("VID: Couldn't read sensor abort VID adjust\n");
 701                         return -1;
 702                 }
 703         } while (vdd_last != svdd);
 704
 705         return 1;
 706 }
 707 #else
 708 int get_serdes_volt(void)
 709 {
 710         return 0;
 711 }
 712
 713 int set_serdes_volt(int svdd)
 714 {
 715         int ret;
 716         u8 brdcfg4;
 717
 718         printf("SVDD changing of RDB\n");
 719
 720         /* Read the BRDCFG54 via CLPD */
 721 #ifndef CONFIG_DM_I2C
 722         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 723                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 724 #else
 725         struct udevice *dev;
 726
 727         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 728         if (!ret)
 729                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 730                                   (void *)&brdcfg4, 1);
 731 #endif
 732
 733         if (ret) {
 734                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 735                 return -1;
 736         }
 737
 738         brdcfg4 = brdcfg4 | 0x08;
 739
 740         /* Write to the BRDCFG4 */
 741 #ifndef CONFIG_DM_I2C
 742         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 743                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 744 #else
 745         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 746                            (void *)&brdcfg4, 1);
 747 #endif
 748
 749         if (ret) {
 750                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 751                 return -1;
 752         }
 753
 754         /* Wait for the volatge to get to the desired value */
 755         udelay(10000);
 756
 757         return 1;
 758 }
 759 #endif
 760
 761 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 762 int board_adjust_vdd(int vdd)
 763 {
 764         int ret = 0;
 765
 766         debug("%s: vdd = %d\n", __func__, vdd);
 767
 768         /* Special settings to be performed when voltage is 900mV */
 769         if (vdd == 900) {
 770                 ret = setup_serdes_volt(vdd);
 771                 if (ret < 0) {
 772                         ret = -1;
 773                         goto exit;
 774                 }
 775         }
 776 exit:
 777         return ret;
 778 }
 779
 780 #if !defined(CONFIG_SPL_BUILD)
 781 int board_init(void)
 782 {
 783         init_final_memctl_regs();
 784 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 785         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 786 #endif
 787
 788         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 789         board_retimer_init();
 790
 791 #ifdef CONFIG_ENV_IS_NOWHERE
 792         gd->env_addr = (ulong)&default_environment[0];
 793 #endif
 794
 795 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 796         /* invert AQR105 IRQ pins polarity */
 797         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 798 #endif
 799
 800 #ifdef CONFIG_FSL_CAAM
 801         sec_init();
 802 #endif
 803 #ifdef CONFIG_FSL_LS_PPA
 804         ppa_init();
 805 #endif
 806
 807 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 808         pci_init();
 809 #endif
 810
 811         return 0;
 812 }
 813
 814 void detail_board_ddr_info(void)
 815 {
 816         puts("\nDDR    ");
 817         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 818         print_ddr_info(0);
 819 }
 820
 821 #ifdef CONFIG_FSL_MC_ENET
 822 void board_quiesce_devices(void)
 823 {
 824         fsl_mc_ldpaa_exit(gd->bd);
 825 }
 826
 827 void fdt_fixup_board_enet(void *fdt)
 828 {
 829         int offset;
 830
 831         offset = fdt_path_offset(fdt, "/fsl-mc");
 832
 833         if (offset < 0)
 834                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 835
 836         if (offset < 0) {
 837                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 838                        __func__, offset);
 839                 return;
 840         }
 841
 842         if (get_mc_boot_status() == 0 &&
 843             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 844                 fdt_status_okay(fdt, offset);
 845         else
 846                 fdt_status_fail(fdt, offset);
 847 }
 848 #endif
 849
 850 #ifdef CONFIG_OF_BOARD_SETUP
 851 void fsl_fdt_fixup_flash(void *fdt)
 852 {
 853         int offset;
 854 #ifdef CONFIG_TFABOOT
 855         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 856         u32 val;
 857 #endif
 858
 859 /*
 860  * IFC-NOR and QSPI are muxed on SoC.
 861  * So disable IFC node in dts if QSPI is enabled or
 862  * disable QSPI node in dts in case QSPI is not enabled.
 863  */
 864
 865 #ifdef CONFIG_TFABOOT
 866         enum boot_src src = get_boot_src();
 867         bool disable_ifc = false;
 868
 869         switch (src) {
 870         case BOOT_SOURCE_IFC_NOR:
 871                 disable_ifc = false;
 872                 break;
 873         case BOOT_SOURCE_QSPI_NOR:
 874                 disable_ifc = true;
 875                 break;
 876         default:
 877                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 878                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 879                         disable_ifc = true;
 880                 break;
 881         }
 882
 883         if (disable_ifc) {
 884                 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 885
 886                 if (offset < 0)
 887                         offset = fdt_path_offset(fdt, "/ifc/nor");
 888         } else {
 889                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 890
 891                 if (offset < 0)
 892                         offset = fdt_path_offset(fdt, "/quadspi");
 893         }
 894
 895 #else
 896 #ifdef CONFIG_FSL_QSPI
 897         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 898
 899         if (offset < 0)
 900                 offset = fdt_path_offset(fdt, "/ifc/nor");
 901 #else
 902         offset = fdt_path_offset(fdt, "/soc/quadspi");
 903
 904         if (offset < 0)
 905                 offset = fdt_path_offset(fdt, "/quadspi");
 906 #endif
 907 #endif
 908         if (offset < 0)
 909                 return;
 910
 911         fdt_status_disabled(fdt, offset);
 912 }
 913
 914 int ft_board_setup(void *blob, bd_t *bd)
 915 {
 916         int i;
 917         u16 mc_memory_bank = 0;
 918
 919         u64 *base;
 920         u64 *size;
 921         u64 mc_memory_base = 0;
 922         u64 mc_memory_size = 0;
 923         u16 total_memory_banks;
 924
 925         ft_cpu_setup(blob, bd);
 926
 927         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 928
 929         if (mc_memory_base != 0)
 930                 mc_memory_bank++;
 931
 932         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 933
 934         base = calloc(total_memory_banks, sizeof(u64));
 935         size = calloc(total_memory_banks, sizeof(u64));
 936
 937         /* fixup DT for the two GPP DDR banks */
 938         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 939                 base[i] = gd->bd->bi_dram[i].start;
 940                 size[i] = gd->bd->bi_dram[i].size;
 941         }
 942
 943 #ifdef CONFIG_RESV_RAM
 944         /* reduce size if reserved memory is within this bank */
 945         if (gd->arch.resv_ram >= base[0] &&
 946             gd->arch.resv_ram < base[0] + size[0])
 947                 size[0] = gd->arch.resv_ram - base[0];
 948         else if (gd->arch.resv_ram >= base[1] &&
 949                  gd->arch.resv_ram < base[1] + size[1])
 950                 size[1] = gd->arch.resv_ram - base[1];
 951 #endif
 952
 953         if (mc_memory_base != 0) {
 954                 for (i = 0; i <= total_memory_banks; i++) {
 955                         if (base[i] == 0 && size[i] == 0) {
 956                                 base[i] = mc_memory_base;
 957                                 size[i] = mc_memory_size;
 958                                 break;
 959                         }
 960                 }
 961         }
 962
 963         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 964
 965         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 966
 967         fsl_fdt_fixup_flash(blob);
 968
 969 #ifdef CONFIG_FSL_MC_ENET
 970         fdt_fixup_board_enet(blob);
 971 #endif
 972
 973         fdt_fixup_icid(blob);
 974
 975         if (is_pb_board())
 976                 fixup_ls1088ardb_pb_banner(blob);
 977
 978         return 0;
 979 }
 980 #endif
 981 #endif /* defined(CONFIG_SPL_BUILD) */
 982
 983 #ifdef CONFIG_TFABOOT
 984 #ifdef CONFIG_MTD_NOR_FLASH
 985 int is_flash_available(void)
 986 {
 987         char *env_hwconfig = env_get("hwconfig");
 988         enum boot_src src = get_boot_src();
 989         int is_nor_flash_available = 1;
 990
 991         switch (src) {
 992         case BOOT_SOURCE_IFC_NOR:
 993                 is_nor_flash_available = 1;
 994                 break;
 995         case BOOT_SOURCE_QSPI_NOR:
 996                 is_nor_flash_available = 0;
 997                 break;
 998         /*
 999          * In Case of SD boot,if qspi is defined in env_hwconfig
1000          * disable nor flash probe.
1001          */
1002         default:
1003                 if (hwconfig_f("qspi", env_hwconfig))
1004                         is_nor_flash_available = 0;
1005                 break;
1006         }
1007         return is_nor_flash_available;
1008 }
1009 #endif
1010
1011 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1012 void *env_sf_get_env_addr(void)
1013 {
1014         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1015 }
1016 #endif
1017 #endif