board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <env.h>
   7 #include <i2c.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ifc.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/io.h>
  17 #include <fdt_support.h>
  18 #include <linux/delay.h>
  19 #include <linux/libfdt.h>
  20 #include <fsl-mc/fsl_mc.h>
  21 #include <env_internal.h>
  22 #include <asm/arch-fsl-layerscape/soc.h>
  23 #include <asm/arch/ppa.h>
  24 #include <hwconfig.h>
  25 #include <asm/arch/fsl_serdes.h>
  26 #include <asm/arch/soc.h>
  27 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  28
  29 #include "../common/qixis.h"
  30 #include "ls1088a_qixis.h"
  31 #include "../common/vid.h"
  32 #include <fsl_immap.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #ifdef CONFIG_TARGET_LS1088AQDS
  37 #ifdef CONFIG_TFABOOT
  38 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  39         {
  40                 "nor0",
  41                 CONFIG_SYS_NOR0_CSPR_EARLY,
  42                 CONFIG_SYS_NOR0_CSPR_EXT,
  43                 CONFIG_SYS_NOR_AMASK,
  44                 CONFIG_SYS_NOR_CSOR,
  45                 {
  46                         CONFIG_SYS_NOR_FTIM0,
  47                         CONFIG_SYS_NOR_FTIM1,
  48                         CONFIG_SYS_NOR_FTIM2,
  49                         CONFIG_SYS_NOR_FTIM3
  50                 },
  51                 0,
  52                 CONFIG_SYS_NOR0_CSPR,
  53                 0,
  54         },
  55         {
  56                 "nor1",
  57                 CONFIG_SYS_NOR1_CSPR_EARLY,
  58                 CONFIG_SYS_NOR0_CSPR_EXT,
  59                 CONFIG_SYS_NOR_AMASK_EARLY,
  60                 CONFIG_SYS_NOR_CSOR,
  61                 {
  62                         CONFIG_SYS_NOR_FTIM0,
  63                         CONFIG_SYS_NOR_FTIM1,
  64                         CONFIG_SYS_NOR_FTIM2,
  65                         CONFIG_SYS_NOR_FTIM3
  66                 },
  67                 0,
  68                 CONFIG_SYS_NOR1_CSPR,
  69                 CONFIG_SYS_NOR_AMASK,
  70         },
  71         {
  72                 "nand",
  73                 CONFIG_SYS_NAND_CSPR,
  74                 CONFIG_SYS_NAND_CSPR_EXT,
  75                 CONFIG_SYS_NAND_AMASK,
  76                 CONFIG_SYS_NAND_CSOR,
  77                 {
  78                         CONFIG_SYS_NAND_FTIM0,
  79                         CONFIG_SYS_NAND_FTIM1,
  80                         CONFIG_SYS_NAND_FTIM2,
  81                         CONFIG_SYS_NAND_FTIM3
  82                 },
  83         },
  84         {
  85                 "fpga",
  86                 CONFIG_SYS_FPGA_CSPR,
  87                 CONFIG_SYS_FPGA_CSPR_EXT,
  88                 SYS_FPGA_AMASK,
  89                 CONFIG_SYS_FPGA_CSOR,
  90                 {
  91                         SYS_FPGA_CS_FTIM0,
  92                         SYS_FPGA_CS_FTIM1,
  93                         SYS_FPGA_CS_FTIM2,
  94                         SYS_FPGA_CS_FTIM3
  95                 },
  96                 0,
  97                 SYS_FPGA_CSPR_FINAL,
  98                 0,
  99         }
 100 };
 101
 102 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 103         {
 104                 "nand",
 105                 CONFIG_SYS_NAND_CSPR,
 106                 CONFIG_SYS_NAND_CSPR_EXT,
 107                 CONFIG_SYS_NAND_AMASK,
 108                 CONFIG_SYS_NAND_CSOR,
 109                 {
 110                         CONFIG_SYS_NAND_FTIM0,
 111                         CONFIG_SYS_NAND_FTIM1,
 112                         CONFIG_SYS_NAND_FTIM2,
 113                         CONFIG_SYS_NAND_FTIM3
 114                 },
 115         },
 116         {
 117                 "reserved",
 118         },
 119         {
 120                 "fpga",
 121                 CONFIG_SYS_FPGA_CSPR,
 122                 CONFIG_SYS_FPGA_CSPR_EXT,
 123                 SYS_FPGA_AMASK,
 124                 CONFIG_SYS_FPGA_CSOR,
 125                 {
 126                         SYS_FPGA_CS_FTIM0,
 127                         SYS_FPGA_CS_FTIM1,
 128                         SYS_FPGA_CS_FTIM2,
 129                         SYS_FPGA_CS_FTIM3
 130                 },
 131                 0,
 132                 SYS_FPGA_CSPR_FINAL,
 133                 0,
 134         }
 135 };
 136
 137 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 138 {
 139         enum boot_src src = get_boot_src();
 140
 141         if (src == BOOT_SOURCE_QSPI_NOR)
 142                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 143         else
 144                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 145
 146         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 147 }
 148 #endif /* CONFIG_TFABOOT */
 149 #endif /* CONFIG_TARGET_LS1088AQDS */
 150
 151 int board_early_init_f(void)
 152 {
 153 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 154         i2c_early_init_f();
 155 #endif
 156         fsl_lsch3_early_init_f();
 157         return 0;
 158 }
 159
 160 #ifdef CONFIG_FSL_QIXIS
 161 unsigned long long get_qixis_addr(void)
 162 {
 163         unsigned long long addr;
 164
 165         if (gd->flags & GD_FLG_RELOC)
 166                 addr = QIXIS_BASE_PHYS;
 167         else
 168                 addr = QIXIS_BASE_PHYS_EARLY;
 169
 170         /*
 171          * IFC address under 256MB is mapped to 0x30000000, any address above
 172          * is mapped to 0x5_10000000 up to 4GB.
 173          */
 174         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 175
 176         return addr;
 177 }
 178 #endif
 179
 180 #if defined(CONFIG_VID)
 181 int init_func_vid(void)
 182 {
 183         if (adjust_vdd(0) < 0)
 184                 printf("core voltage not adjusted\n");
 185
 186         return 0;
 187 }
 188 #endif
 189
 190 int is_pb_board(void)
 191 {
 192         u8 board_id;
 193
 194         board_id = QIXIS_READ(id);
 195         if (board_id == LS1088ARDB_PB_BOARD)
 196                 return 1;
 197         else
 198                 return 0;
 199 }
 200
 201 int fixup_ls1088ardb_pb_banner(void *fdt)
 202 {
 203         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 204
 205         return 0;
 206 }
 207
 208 #if !defined(CONFIG_SPL_BUILD)
 209 int checkboard(void)
 210 {
 211 #ifdef CONFIG_TFABOOT
 212         enum boot_src src = get_boot_src();
 213 #endif
 214         char buf[64];
 215         u8 sw;
 216         static const char *const freq[] = {"100", "125", "156.25",
 217                                             "100 separate SSCG"};
 218         int clock;
 219
 220 #ifdef CONFIG_TARGET_LS1088AQDS
 221         printf("Board: LS1088A-QDS, ");
 222 #else
 223         if (is_pb_board())
 224                 printf("Board: LS1088ARDB-PB, ");
 225         else
 226                 printf("Board: LS1088A-RDB, ");
 227 #endif
 228
 229         sw = QIXIS_READ(arch);
 230         printf("Board Arch: V%d, ", sw >> 4);
 231
 232 #ifdef CONFIG_TARGET_LS1088AQDS
 233         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 234 #else
 235         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 236 #endif
 237
 238         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 239
 240         sw = QIXIS_READ(brdcfg[0]);
 241         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 242
 243 #ifdef CONFIG_TFABOOT
 244         if (src == BOOT_SOURCE_SD_MMC)
 245                 puts("SD card\n");
 246 #else
 247 #ifdef CONFIG_SD_BOOT
 248         puts("SD card\n");
 249 #endif
 250 #endif /* CONFIG_TFABOOT */
 251         switch (sw) {
 252 #ifdef CONFIG_TARGET_LS1088AQDS
 253         case 0:
 254         case 1:
 255         case 2:
 256         case 3:
 257         case 4:
 258         case 5:
 259         case 6:
 260         case 7:
 261                 printf("vBank: %d\n", sw);
 262                 break;
 263         case 8:
 264                 puts("PromJet\n");
 265                 break;
 266         case 15:
 267                 puts("IFCCard\n");
 268                 break;
 269         case 14:
 270 #else
 271         case 0:
 272 #endif
 273                 puts("QSPI:");
 274                 sw = QIXIS_READ(brdcfg[0]);
 275                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 276                 if (sw == 0 || sw == 4)
 277                         puts("0\n");
 278                 else if (sw == 1)
 279                         puts("1\n");
 280                 else
 281                         puts("EMU\n");
 282                 break;
 283
 284         default:
 285                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 286                 break;
 287         }
 288
 289 #ifdef CONFIG_TARGET_LS1088AQDS
 290         printf("FPGA: v%d (%s), build %d",
 291                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 292                (int)qixis_read_minor());
 293         /* the timestamp string contains "\n" at the end */
 294         printf(" on %s", qixis_read_time(buf));
 295 #else
 296         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 297 #endif
 298
 299         /*
 300          * Display the actual SERDES reference clocks as configured by the
 301          * dip switches on the board.  Note that the SWx registers could
 302          * technically be set to force the reference clocks to match the
 303          * values that the SERDES expects (or vice versa).  For now, however,
 304          * we just display both values and hope the user notices when they
 305          * don't match.
 306          */
 307         puts("SERDES1 Reference : ");
 308         sw = QIXIS_READ(brdcfg[2]);
 309         clock = (sw >> 6) & 3;
 310         printf("Clock1 = %sMHz ", freq[clock]);
 311         clock = (sw >> 4) & 3;
 312         printf("Clock2 = %sMHz", freq[clock]);
 313
 314         puts("\nSERDES2 Reference : ");
 315         clock = (sw >> 2) & 3;
 316         printf("Clock1 = %sMHz ", freq[clock]);
 317         clock = (sw >> 0) & 3;
 318         printf("Clock2 = %sMHz\n", freq[clock]);
 319
 320         return 0;
 321 }
 322 #endif
 323
 324 bool if_board_diff_clk(void)
 325 {
 326 #ifdef CONFIG_TARGET_LS1088AQDS
 327         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 328         return diff_conf & 0x40;
 329 #else
 330         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 331         return diff_conf & 0x80;
 332 #endif
 333 }
 334
 335 unsigned long get_board_sys_clk(void)
 336 {
 337         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 338
 339         switch (sysclk_conf & 0x0f) {
 340         case QIXIS_SYSCLK_83:
 341                 return 83333333;
 342         case QIXIS_SYSCLK_100:
 343                 return 100000000;
 344         case QIXIS_SYSCLK_125:
 345                 return 125000000;
 346         case QIXIS_SYSCLK_133:
 347                 return 133333333;
 348         case QIXIS_SYSCLK_150:
 349                 return 150000000;
 350         case QIXIS_SYSCLK_160:
 351                 return 160000000;
 352         case QIXIS_SYSCLK_166:
 353                 return 166666666;
 354         }
 355
 356         return 66666666;
 357 }
 358
 359 unsigned long get_board_ddr_clk(void)
 360 {
 361         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 362
 363         if (if_board_diff_clk())
 364                 return get_board_sys_clk();
 365         switch ((ddrclk_conf & 0x30) >> 4) {
 366         case QIXIS_DDRCLK_100:
 367                 return 100000000;
 368         case QIXIS_DDRCLK_125:
 369                 return 125000000;
 370         case QIXIS_DDRCLK_133:
 371                 return 133333333;
 372         }
 373
 374         return 66666666;
 375 }
 376
 377 int select_i2c_ch_pca9547(u8 ch)
 378 {
 379         int ret;
 380
 381 #ifndef CONFIG_DM_I2C
 382         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 383 #else
 384         struct udevice *dev;
 385
 386         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
 387         if (!ret)
 388                 ret = dm_i2c_write(dev, 0, &ch, 1);
 389 #endif
 390         if (ret) {
 391                 puts("PCA: failed to select proper channel\n");
 392                 return ret;
 393         }
 394
 395         return 0;
 396 }
 397
 398 #if !defined(CONFIG_SPL_BUILD)
 399 void board_retimer_init(void)
 400 {
 401         u8 reg;
 402
 403         /* Retimer is connected to I2C1_CH5 */
 404         select_i2c_ch_pca9547(I2C_MUX_CH5);
 405
 406         /* Access to Control/Shared register */
 407         reg = 0x0;
 408 #ifndef CONFIG_DM_I2C
 409         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 410 #else
 411         struct udevice *dev;
 412
 413         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 414         dm_i2c_write(dev, 0xff, &reg, 1);
 415 #endif
 416
 417         /* Read device revision and ID */
 418 #ifndef CONFIG_DM_I2C
 419         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 420 #else
 421         dm_i2c_read(dev, 1, &reg, 1);
 422 #endif
 423         debug("Retimer version id = 0x%x\n", reg);
 424
 425         /* Enable Broadcast. All writes target all channel register sets */
 426         reg = 0x0c;
 427 #ifndef CONFIG_DM_I2C
 428         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 429 #else
 430         dm_i2c_write(dev, 0xff, &reg, 1);
 431 #endif
 432
 433         /* Reset Channel Registers */
 434 #ifndef CONFIG_DM_I2C
 435         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 436 #else
 437         dm_i2c_read(dev, 0, &reg, 1);
 438 #endif
 439         reg |= 0x4;
 440 #ifndef CONFIG_DM_I2C
 441         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 442 #else
 443         dm_i2c_write(dev, 0, &reg, 1);
 444 #endif
 445
 446         /* Set data rate as 10.3125 Gbps */
 447         reg = 0x90;
 448 #ifndef CONFIG_DM_I2C
 449         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 450 #else
 451         dm_i2c_write(dev, 0x60, &reg, 1);
 452 #endif
 453         reg = 0xb3;
 454 #ifndef CONFIG_DM_I2C
 455         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 456 #else
 457         dm_i2c_write(dev, 0x61, &reg, 1);
 458 #endif
 459         reg = 0x90;
 460 #ifndef CONFIG_DM_I2C
 461         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 462 #else
 463         dm_i2c_write(dev, 0x62, &reg, 1);
 464 #endif
 465         reg = 0xb3;
 466 #ifndef CONFIG_DM_I2C
 467         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 468 #else
 469         dm_i2c_write(dev, 0x63, &reg, 1);
 470 #endif
 471         reg = 0xcd;
 472 #ifndef CONFIG_DM_I2C
 473         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 474 #else
 475         dm_i2c_write(dev, 0x64, &reg, 1);
 476 #endif
 477
 478         /* Select VCO Divider to full rate (000) */
 479 #ifndef CONFIG_DM_I2C
 480         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 481 #else
 482         dm_i2c_read(dev, 0x2F, &reg, 1);
 483 #endif
 484         reg &= 0x0f;
 485         reg |= 0x70;
 486 #ifndef CONFIG_DM_I2C
 487         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 488 #else
 489         dm_i2c_write(dev, 0x2F, &reg, 1);
 490 #endif
 491
 492 #ifdef  CONFIG_TARGET_LS1088AQDS
 493         /* Retimer is connected to I2C1_CH5 */
 494         select_i2c_ch_pca9547(I2C_MUX_CH5);
 495
 496         /* Access to Control/Shared register */
 497         reg = 0x0;
 498 #ifndef CONFIG_DM_I2C
 499         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 500 #else
 501         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 502         dm_i2c_write(dev, 0xff, &reg, 1);
 503 #endif
 504
 505         /* Read device revision and ID */
 506 #ifndef CONFIG_DM_I2C
 507         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 508 #else
 509         dm_i2c_read(dev, 1, &reg, 1);
 510 #endif
 511         debug("Retimer version id = 0x%x\n", reg);
 512
 513         /* Enable Broadcast. All writes target all channel register sets */
 514         reg = 0x0c;
 515 #ifndef CONFIG_DM_I2C
 516         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 517 #else
 518         dm_i2c_write(dev, 0xff, &reg, 1);
 519 #endif
 520
 521         /* Reset Channel Registers */
 522 #ifndef CONFIG_DM_I2C
 523         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 524 #else
 525         dm_i2c_read(dev, 0, &reg, 1);
 526 #endif
 527         reg |= 0x4;
 528 #ifndef CONFIG_DM_I2C
 529         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 530 #else
 531         dm_i2c_write(dev, 0, &reg, 1);
 532 #endif
 533
 534         /* Set data rate as 10.3125 Gbps */
 535         reg = 0x90;
 536 #ifndef CONFIG_DM_I2C
 537         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 538 #else
 539         dm_i2c_write(dev, 0x60, &reg, 1);
 540 #endif
 541         reg = 0xb3;
 542 #ifndef CONFIG_DM_I2C
 543         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 544 #else
 545         dm_i2c_write(dev, 0x61, &reg, 1);
 546 #endif
 547         reg = 0x90;
 548 #ifndef CONFIG_DM_I2C
 549         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 550 #else
 551         dm_i2c_write(dev, 0x62, &reg, 1);
 552 #endif
 553         reg = 0xb3;
 554 #ifndef CONFIG_DM_I2C
 555         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 556 #else
 557         dm_i2c_write(dev, 0x63, &reg, 1);
 558 #endif
 559         reg = 0xcd;
 560 #ifndef CONFIG_DM_I2C
 561         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 562 #else
 563         dm_i2c_write(dev, 0x64, &reg, 1);
 564 #endif
 565
 566         /* Select VCO Divider to full rate (000) */
 567 #ifndef CONFIG_DM_I2C
 568         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 569 #else
 570         dm_i2c_read(dev, 0x2F, &reg, 1);
 571 #endif
 572         reg &= 0x0f;
 573         reg |= 0x70;
 574 #ifndef CONFIG_DM_I2C
 575         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 576 #else
 577         dm_i2c_write(dev, 0x2F, &reg, 1);
 578 #endif
 579
 580 #endif
 581         /*return the default channel*/
 582         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 583 }
 584
 585 #ifdef CONFIG_MISC_INIT_R
 586 int misc_init_r(void)
 587 {
 588 #ifdef CONFIG_TARGET_LS1088ARDB
 589         u8 brdcfg5;
 590
 591         if (hwconfig("esdhc-force-sd")) {
 592                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 593                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 594                 brdcfg5 |= BRDCFG5_FORCE_SD;
 595                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 596         }
 597 #endif
 598
 599 #ifdef CONFIG_TARGET_LS1088AQDS
 600          u8 brdcfg4, brdcfg5;
 601
 602         if (hwconfig("dspi-on-board")) {
 603                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 604                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 605                 brdcfg4 |= BRDCFG4_SPI;
 606                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 607
 608                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 609                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 610                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 611                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 612         } else if (hwconfig("dspi-off-board")) {
 613                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 614                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 615                 brdcfg4 |= BRDCFG4_SPI;
 616                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 617
 618                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 619                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 620                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 621                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 622         }
 623 #endif
 624         return 0;
 625 }
 626 #endif
 627 #endif
 628
 629 int i2c_multiplexer_select_vid_channel(u8 channel)
 630 {
 631         return select_i2c_ch_pca9547(channel);
 632 }
 633
 634 #ifdef CONFIG_TARGET_LS1088AQDS
 635 /* read the current value(SVDD) of the LTM Regulator Voltage */
 636 int get_serdes_volt(void)
 637 {
 638         int  ret, vcode = 0;
 639         u8 chan = PWM_CHANNEL0;
 640
 641         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 642 #ifndef CONFIG_DM_I2C
 643         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 644                         PMBUS_CMD_PAGE, 1, &chan, 1);
 645 #else
 646         struct udevice *dev;
 647
 648         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 649         if (!ret)
 650                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 651                                    &chan, 1);
 652 #endif
 653
 654         if (ret) {
 655                 printf("VID: failed to select VDD Page 0\n");
 656                 return ret;
 657         }
 658
 659         /* Read the output voltage using PMBus command READ_VOUT */
 660 #ifndef CONFIG_DM_I2C
 661         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 662                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 663 #else
 664         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 665 #endif
 666         if (ret) {
 667                 printf("VID: failed to read the volatge\n");
 668                 return ret;
 669         }
 670
 671         return vcode;
 672 }
 673
 674 int set_serdes_volt(int svdd)
 675 {
 676         int ret, vdd_last;
 677         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 678                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 679
 680         /* Write the desired voltage code to the SVDD regulator */
 681 #ifndef CONFIG_DM_I2C
 682         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 683                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 684 #else
 685         struct udevice *dev;
 686
 687         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 688         if (!ret)
 689                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 690                                    (void *)&buff, 5);
 691 #endif
 692         if (ret) {
 693                 printf("VID: I2C failed to write to the volatge regulator\n");
 694                 return -1;
 695         }
 696
 697         /* Wait for the volatge to get to the desired value */
 698         do {
 699                 vdd_last = get_serdes_volt();
 700                 if (vdd_last < 0) {
 701                         printf("VID: Couldn't read sensor abort VID adjust\n");
 702                         return -1;
 703                 }
 704         } while (vdd_last != svdd);
 705
 706         return 1;
 707 }
 708 #else
 709 int get_serdes_volt(void)
 710 {
 711         return 0;
 712 }
 713
 714 int set_serdes_volt(int svdd)
 715 {
 716         int ret;
 717         u8 brdcfg4;
 718
 719         printf("SVDD changing of RDB\n");
 720
 721         /* Read the BRDCFG54 via CLPD */
 722 #ifndef CONFIG_DM_I2C
 723         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 724                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 725 #else
 726         struct udevice *dev;
 727
 728         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 729         if (!ret)
 730                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 731                                   (void *)&brdcfg4, 1);
 732 #endif
 733
 734         if (ret) {
 735                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 736                 return -1;
 737         }
 738
 739         brdcfg4 = brdcfg4 | 0x08;
 740
 741         /* Write to the BRDCFG4 */
 742 #ifndef CONFIG_DM_I2C
 743         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 744                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 745 #else
 746         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 747                            (void *)&brdcfg4, 1);
 748 #endif
 749
 750         if (ret) {
 751                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 752                 return -1;
 753         }
 754
 755         /* Wait for the volatge to get to the desired value */
 756         udelay(10000);
 757
 758         return 1;
 759 }
 760 #endif
 761
 762 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 763 int board_adjust_vdd(int vdd)
 764 {
 765         int ret = 0;
 766
 767         debug("%s: vdd = %d\n", __func__, vdd);
 768
 769         /* Special settings to be performed when voltage is 900mV */
 770         if (vdd == 900) {
 771                 ret = setup_serdes_volt(vdd);
 772                 if (ret < 0) {
 773                         ret = -1;
 774                         goto exit;
 775                 }
 776         }
 777 exit:
 778         return ret;
 779 }
 780
 781 #if !defined(CONFIG_SPL_BUILD)
 782 int board_init(void)
 783 {
 784         init_final_memctl_regs();
 785 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 786         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 787 #endif
 788
 789         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 790         board_retimer_init();
 791
 792 #ifdef CONFIG_ENV_IS_NOWHERE
 793         gd->env_addr = (ulong)&default_environment[0];
 794 #endif
 795
 796 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 797         /* invert AQR105 IRQ pins polarity */
 798         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 799 #endif
 800
 801 #ifdef CONFIG_FSL_CAAM
 802         sec_init();
 803 #endif
 804 #ifdef CONFIG_FSL_LS_PPA
 805         ppa_init();
 806 #endif
 807
 808 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 809         pci_init();
 810 #endif
 811
 812         return 0;
 813 }
 814
 815 void detail_board_ddr_info(void)
 816 {
 817         puts("\nDDR    ");
 818         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 819         print_ddr_info(0);
 820 }
 821
 822 #ifdef CONFIG_FSL_MC_ENET
 823 void board_quiesce_devices(void)
 824 {
 825         fsl_mc_ldpaa_exit(gd->bd);
 826 }
 827
 828 void fdt_fixup_board_enet(void *fdt)
 829 {
 830         int offset;
 831
 832         offset = fdt_path_offset(fdt, "/fsl-mc");
 833
 834         if (offset < 0)
 835                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 836
 837         if (offset < 0) {
 838                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 839                        __func__, offset);
 840                 return;
 841         }
 842
 843         if (get_mc_boot_status() == 0 &&
 844             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 845                 fdt_status_okay(fdt, offset);
 846         else
 847                 fdt_status_fail(fdt, offset);
 848 }
 849 #endif
 850
 851 #ifdef CONFIG_OF_BOARD_SETUP
 852 void fsl_fdt_fixup_flash(void *fdt)
 853 {
 854         int offset;
 855 #ifdef CONFIG_TFABOOT
 856         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 857         u32 val;
 858 #endif
 859
 860 /*
 861  * IFC-NOR and QSPI are muxed on SoC.
 862  * So disable IFC node in dts if QSPI is enabled or
 863  * disable QSPI node in dts in case QSPI is not enabled.
 864  */
 865
 866 #ifdef CONFIG_TFABOOT
 867         enum boot_src src = get_boot_src();
 868         bool disable_ifc = false;
 869
 870         switch (src) {
 871         case BOOT_SOURCE_IFC_NOR:
 872                 disable_ifc = false;
 873                 break;
 874         case BOOT_SOURCE_QSPI_NOR:
 875                 disable_ifc = true;
 876                 break;
 877         default:
 878                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 879                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 880                         disable_ifc = true;
 881                 break;
 882         }
 883
 884         if (disable_ifc) {
 885                 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 886
 887                 if (offset < 0)
 888                         offset = fdt_path_offset(fdt, "/ifc/nor");
 889         } else {
 890                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 891
 892                 if (offset < 0)
 893                         offset = fdt_path_offset(fdt, "/quadspi");
 894         }
 895
 896 #else
 897 #ifdef CONFIG_FSL_QSPI
 898         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 899
 900         if (offset < 0)
 901                 offset = fdt_path_offset(fdt, "/ifc/nor");
 902 #else
 903         offset = fdt_path_offset(fdt, "/soc/quadspi");
 904
 905         if (offset < 0)
 906                 offset = fdt_path_offset(fdt, "/quadspi");
 907 #endif
 908 #endif
 909         if (offset < 0)
 910                 return;
 911
 912         fdt_status_disabled(fdt, offset);
 913 }
 914
 915 int ft_board_setup(void *blob, bd_t *bd)
 916 {
 917         int i;
 918         u16 mc_memory_bank = 0;
 919
 920         u64 *base;
 921         u64 *size;
 922         u64 mc_memory_base = 0;
 923         u64 mc_memory_size = 0;
 924         u16 total_memory_banks;
 925
 926         ft_cpu_setup(blob, bd);
 927
 928         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 929
 930         if (mc_memory_base != 0)
 931                 mc_memory_bank++;
 932
 933         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 934
 935         base = calloc(total_memory_banks, sizeof(u64));
 936         size = calloc(total_memory_banks, sizeof(u64));
 937
 938         /* fixup DT for the two GPP DDR banks */
 939         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 940                 base[i] = gd->bd->bi_dram[i].start;
 941                 size[i] = gd->bd->bi_dram[i].size;
 942         }
 943
 944 #ifdef CONFIG_RESV_RAM
 945         /* reduce size if reserved memory is within this bank */
 946         if (gd->arch.resv_ram >= base[0] &&
 947             gd->arch.resv_ram < base[0] + size[0])
 948                 size[0] = gd->arch.resv_ram - base[0];
 949         else if (gd->arch.resv_ram >= base[1] &&
 950                  gd->arch.resv_ram < base[1] + size[1])
 951                 size[1] = gd->arch.resv_ram - base[1];
 952 #endif
 953
 954         if (mc_memory_base != 0) {
 955                 for (i = 0; i <= total_memory_banks; i++) {
 956                         if (base[i] == 0 && size[i] == 0) {
 957                                 base[i] = mc_memory_base;
 958                                 size[i] = mc_memory_size;
 959                                 break;
 960                         }
 961                 }
 962         }
 963
 964         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 965
 966         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 967
 968         fsl_fdt_fixup_flash(blob);
 969
 970 #ifdef CONFIG_FSL_MC_ENET
 971         fdt_fixup_board_enet(blob);
 972 #endif
 973
 974         fdt_fixup_icid(blob);
 975
 976         if (is_pb_board())
 977                 fixup_ls1088ardb_pb_banner(blob);
 978
 979         return 0;
 980 }
 981 #endif
 982 #endif /* defined(CONFIG_SPL_BUILD) */
 983
 984 #ifdef CONFIG_TFABOOT
 985 #ifdef CONFIG_MTD_NOR_FLASH
 986 int is_flash_available(void)
 987 {
 988         char *env_hwconfig = env_get("hwconfig");
 989         enum boot_src src = get_boot_src();
 990         int is_nor_flash_available = 1;
 991
 992         switch (src) {
 993         case BOOT_SOURCE_IFC_NOR:
 994                 is_nor_flash_available = 1;
 995                 break;
 996         case BOOT_SOURCE_QSPI_NOR:
 997                 is_nor_flash_available = 0;
 998                 break;
 999         /*
1000          * In Case of SD boot,if qspi is defined in env_hwconfig
1001          * disable nor flash probe.
1002          */
1003         default:
1004                 if (hwconfig_f("qspi", env_hwconfig))
1005                         is_nor_flash_available = 0;
1006                 break;
1007         }
1008         return is_nor_flash_available;
1009 }
1010 #endif
1011
1012 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1013 void *env_sf_get_env_addr(void)
1014 {
1015         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1016 }
1017 #endif
1018 #endif