board/freescale/ls1088a/eth_ls1088aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <env.h>
   9 #include <log.h>
  10 #include <net.h>
  11 #include <netdev.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <hwconfig.h>
  15 #include <fsl_mdio.h>
  16 #include <malloc.h>
  17 #include <phy.h>
  18 #include <fm_eth.h>
  19 #include <i2c.h>
  20 #include <miiphy.h>
  21 #include <fsl-mc/fsl_mc.h>
  22 #include <fsl-mc/ldpaa_wriop.h>
  23 #include <linux/delay.h>
  24
  25 #include "../common/qixis.h"
  26
  27 #include "ls1088a_qixis.h"
  28
  29 #ifdef CONFIG_FSL_MC_ENET
  30
  31 #define SFP_TX          0
  32
  33  /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  34  *   Bank 1 -> Lanes A, B, C, D,
  35  *   Bank 2 -> Lanes A,B, C, D,
  36  */
  37
  38  /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
  39   * means that the mapping must be determined dynamically, or that the lane
  40   * maps to something other than a board slot.
  41   */
  42
  43 static u8 lane_to_slot_fsm1[] = {
  44         0, 0, 0, 0, 0, 0, 0, 0
  45 };
  46
  47 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  48  * housed.
  49  */
  50
  51 static int xqsgii_riser_phy_addr[] = {
  52         XQSGMII_CARD_PHY1_PORT0_ADDR,
  53         XQSGMII_CARD_PHY2_PORT0_ADDR,
  54         XQSGMII_CARD_PHY3_PORT0_ADDR,
  55         XQSGMII_CARD_PHY4_PORT0_ADDR,
  56         XQSGMII_CARD_PHY3_PORT2_ADDR,
  57         XQSGMII_CARD_PHY1_PORT2_ADDR,
  58         XQSGMII_CARD_PHY4_PORT2_ADDR,
  59         XQSGMII_CARD_PHY2_PORT2_ADDR,
  60 };
  61
  62 static int sgmii_riser_phy_addr[] = {
  63         SGMII_CARD_PORT1_PHY_ADDR,
  64         SGMII_CARD_PORT2_PHY_ADDR,
  65         SGMII_CARD_PORT3_PHY_ADDR,
  66         SGMII_CARD_PORT4_PHY_ADDR,
  67 };
  68
  69 /* Slot2 does not have EMI connections */
  70 #define EMI_NONE        0xFF
  71 #define EMI1_RGMII1     0
  72 #define EMI1_RGMII2     1
  73 #define EMI1_SLOT1      2
  74
  75 static const char * const mdio_names[] = {
  76         "LS1088A_QDS_MDIO0",
  77         "LS1088A_QDS_MDIO1",
  78         "LS1088A_QDS_MDIO2",
  79         DEFAULT_WRIOP_MDIO2_NAME,
  80 };
  81
  82 struct ls1088a_qds_mdio {
  83         u8 muxval;
  84         struct mii_dev *realbus;
  85 };
  86
  87 struct reg_pair {
  88         uint addr;
  89         u8 *val;
  90 };
  91
  92 static void sgmii_configure_repeater(int dpmac)
  93 {
  94         struct mii_dev *bus;
  95         uint8_t a = 0xf;
  96         int i, j, k, ret;
  97         unsigned short value;
  98         const char *dev = "LS1088A_QDS_MDIO2";
  99         int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
 100         int i2c_phy_addr = 0;
 101         int phy_addr = 0;
 102
 103         uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
 104         uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 105         uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 106         uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 107
 108         u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
 109         struct reg_pair reg_pair[10] = {
 110                 {6, &reg_val[0]}, {4, &reg_val[1]},
 111                 {8, &reg_val[2]}, {0xf, NULL},
 112                 {0x11, NULL}, {0x16, NULL},
 113                 {0x18, NULL}, {0x23, &reg_val[3]},
 114                 {0x2d, &reg_val[4]}, {4, &reg_val[5]},
 115         };
 116 #ifdef CONFIG_DM_I2C
 117         struct udevice *udev;
 118 #endif
 119
 120         /* Set I2c to Slot 1 */
 121 #ifndef CONFIG_DM_I2C
 122         ret = i2c_write(0x77, 0, 0, &a, 1);
 123 #else
 124         ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
 125         if (!ret)
 126                 ret = dm_i2c_write(udev, 0, &a, 1);
 127 #endif
 128         if (ret)
 129                 goto error;
 130
 131         switch (dpmac) {
 132         case 1:
 133                 i2c_phy_addr = i2c_addr[1];
 134                 phy_addr = 4;
 135                 break;
 136         case 2:
 137                 i2c_phy_addr = i2c_addr[0];
 138                 phy_addr = 0;
 139                 break;
 140         case 3:
 141                 i2c_phy_addr = i2c_addr[3];
 142                 phy_addr = 0xc;
 143                 break;
 144         case 7:
 145                 i2c_phy_addr = i2c_addr[2];
 146                 phy_addr = 8;
 147                 break;
 148         }
 149
 150         /* Check the PHY status */
 151         ret = miiphy_set_current_dev(dev);
 152         if (ret > 0)
 153                 goto error;
 154
 155         bus = mdio_get_current_dev();
 156         debug("Reading from bus %s\n", bus->name);
 157
 158         ret = miiphy_write(dev, phy_addr, 0x1f, 3);
 159         if (ret > 0)
 160                 goto error;
 161
 162         mdelay(10);
 163         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 164         if (ret > 0)
 165                         goto error;
 166
 167         mdelay(10);
 168
 169         if ((value & 0xfff) == 0x401) {
 170                 miiphy_write(dev, phy_addr, 0x1f, 0);
 171                 printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
 172                 return;
 173         }
 174
 175 #ifdef CONFIG_DM_I2C
 176         i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
 177 #endif
 178
 179         for (i = 0; i < 4; i++) {
 180                 for (j = 0; j < 4; j++) {
 181                         reg_pair[3].val = &ch_a_eq[i];
 182                         reg_pair[4].val = &ch_a_ctl2[j];
 183                         reg_pair[5].val = &ch_b_eq[i];
 184                         reg_pair[6].val = &ch_b_ctl2[j];
 185                         for (k = 0; k < 10; k++) {
 186 #ifndef CONFIG_DM_I2C
 187                                 ret = i2c_write(i2c_phy_addr,
 188                                                 reg_pair[k].addr,
 189                                                 1, reg_pair[k].val, 1);
 190 #else
 191                                 ret = i2c_get_chip_for_busnum(0,
 192                                                               i2c_phy_addr,
 193                                                               1, &udev);
 194                                 if (!ret)
 195                                         ret = dm_i2c_write(udev,
 196                                                            reg_pair[k].addr,
 197                                                            reg_pair[k].val, 1);
 198 #endif
 199                                 if (ret)
 200                                         goto error;
 201                         }
 202
 203                         mdelay(100);
 204                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 205                         if (ret > 0)
 206                                 goto error;
 207
 208                         mdelay(100);
 209                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 210                         if (ret > 0)
 211                                 goto error;
 212
 213                         if ((value & 0xfff) == 0x401) {
 214                                 printf("DPMAC %d :PHY is configured ",
 215                                        dpmac);
 216                                 printf("after setting repeater 0x%x\n",
 217                                        value);
 218                                 i = 5;
 219                                 j = 5;
 220                         } else {
 221                                 printf("DPMAC %d :PHY is failed to ",
 222                                        dpmac);
 223                                 printf("configure the repeater 0x%x\n", value);
 224                         }
 225                 }
 226         }
 227         miiphy_write(dev, phy_addr, 0x1f, 0);
 228 error:
 229         if (ret)
 230                 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
 231         return;
 232 }
 233
 234 static void qsgmii_configure_repeater(int dpmac)
 235 {
 236         uint8_t a = 0xf;
 237         int i, j, k;
 238         int i2c_phy_addr = 0;
 239         int phy_addr = 0;
 240         int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
 241
 242         uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
 243         uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 244         uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 245         uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 246
 247         u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
 248         struct reg_pair reg_pair[10] = {
 249                 {6, &reg_val[0]}, {4, &reg_val[1]},
 250                 {8, &reg_val[2]}, {0xf, NULL},
 251                 {0x11, NULL}, {0x16, NULL},
 252                 {0x18, NULL}, {0x23, &reg_val[3]},
 253                 {0x2d, &reg_val[4]}, {4, &reg_val[5]},
 254         };
 255
 256         const char *dev = mdio_names[EMI1_SLOT1];
 257         int ret = 0;
 258         unsigned short value;
 259 #ifdef CONFIG_DM_I2C
 260         struct udevice *udev;
 261 #endif
 262
 263         /* Set I2c to Slot 1 */
 264 #ifndef CONFIG_DM_I2C
 265         ret = i2c_write(0x77, 0, 0, &a, 1);
 266 #else
 267         ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
 268         if (!ret)
 269                 ret = dm_i2c_write(udev, 0, &a, 1);
 270 #endif
 271         if (ret)
 272                 goto error;
 273
 274         switch (dpmac) {
 275         case 7:
 276         case 8:
 277         case 9:
 278         case 10:
 279                 i2c_phy_addr = i2c_addr[2];
 280                 phy_addr = 8;
 281                 break;
 282
 283         case 3:
 284         case 4:
 285         case 5:
 286         case 6:
 287                 i2c_phy_addr = i2c_addr[3];
 288                 phy_addr = 0xc;
 289                 break;
 290         }
 291
 292         /* Check the PHY status */
 293         ret = miiphy_set_current_dev(dev);
 294         ret = miiphy_write(dev, phy_addr, 0x1f, 3);
 295         mdelay(10);
 296         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 297         mdelay(10);
 298         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 299         mdelay(10);
 300         if ((value & 0xf) == 0xf) {
 301                 miiphy_write(dev, phy_addr, 0x1f, 0);
 302                 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
 303                 return;
 304         }
 305
 306 #ifdef CONFIG_DM_I2C
 307         i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
 308 #endif
 309
 310         for (i = 0; i < 4; i++) {
 311                 for (j = 0; j < 4; j++) {
 312                         reg_pair[3].val = &ch_a_eq[i];
 313                         reg_pair[4].val = &ch_a_ctl2[j];
 314                         reg_pair[5].val = &ch_b_eq[i];
 315                         reg_pair[6].val = &ch_b_ctl2[j];
 316
 317                         for (k = 0; k < 10; k++) {
 318 #ifndef CONFIG_DM_I2C
 319                                 ret = i2c_write(i2c_phy_addr,
 320                                                 reg_pair[k].addr,
 321                                                 1, reg_pair[k].val, 1);
 322 #else
 323                                 ret = i2c_get_chip_for_busnum(0,
 324                                                               i2c_addr[dpmac],
 325                                                               1, &udev);
 326                                 if (!ret)
 327                                         ret = dm_i2c_write(udev,
 328                                                            reg_pair[k].addr,
 329                                                            reg_pair[k].val, 1);
 330 #endif
 331                                 if (ret)
 332                                         goto error;
 333                         }
 334
 335                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 336                         if (ret > 0)
 337                                 goto error;
 338                         mdelay(1);
 339                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 340                         if (ret > 0)
 341                                 goto error;
 342                         mdelay(10);
 343                         if ((value & 0xf) == 0xf) {
 344                                 miiphy_write(dev, phy_addr, 0x1f, 0);
 345                                 printf("DPMAC %d :PHY is ..... Configured\n",
 346                                        dpmac);
 347                                 return;
 348                         }
 349                 }
 350         }
 351 error:
 352         printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
 353         return;
 354 }
 355
 356 static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
 357 {
 358         return mdio_names[muxval];
 359 }
 360
 361 struct mii_dev *mii_dev_for_muxval(u8 muxval)
 362 {
 363         struct mii_dev *bus;
 364         const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
 365
 366         if (!name) {
 367                 printf("No bus for muxval %x\n", muxval);
 368                 return NULL;
 369         }
 370
 371         bus = miiphy_get_dev_by_name(name);
 372
 373         if (!bus) {
 374                 printf("No bus by name %s\n", name);
 375                 return NULL;
 376         }
 377
 378         return bus;
 379 }
 380
 381 static void ls1088a_qds_enable_SFP_TX(u8 muxval)
 382 {
 383         u8 brdcfg9;
 384
 385         brdcfg9 = QIXIS_READ(brdcfg[9]);
 386         brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
 387         brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
 388         QIXIS_WRITE(brdcfg[9], brdcfg9);
 389 }
 390
 391 static void ls1088a_qds_mux_mdio(u8 muxval)
 392 {
 393         u8 brdcfg4;
 394
 395         if (muxval <= 5) {
 396                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 397                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 398                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 399                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 400         }
 401 }
 402
 403 static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
 404                                  int devad, int regnum)
 405 {
 406         struct ls1088a_qds_mdio *priv = bus->priv;
 407
 408         ls1088a_qds_mux_mdio(priv->muxval);
 409
 410         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 411 }
 412
 413 static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 414                                   int regnum, u16 value)
 415 {
 416         struct ls1088a_qds_mdio *priv = bus->priv;
 417
 418         ls1088a_qds_mux_mdio(priv->muxval);
 419
 420         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 421 }
 422
 423 static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
 424 {
 425         struct ls1088a_qds_mdio *priv = bus->priv;
 426
 427         return priv->realbus->reset(priv->realbus);
 428 }
 429
 430 static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
 431 {
 432         struct ls1088a_qds_mdio *pmdio;
 433         struct mii_dev *bus = mdio_alloc();
 434
 435         if (!bus) {
 436                 printf("Failed to allocate ls1088a_qds MDIO bus\n");
 437                 return -1;
 438         }
 439
 440         pmdio = malloc(sizeof(*pmdio));
 441         if (!pmdio) {
 442                 printf("Failed to allocate ls1088a_qds private data\n");
 443                 free(bus);
 444                 return -1;
 445         }
 446
 447         bus->read = ls1088a_qds_mdio_read;
 448         bus->write = ls1088a_qds_mdio_write;
 449         bus->reset = ls1088a_qds_mdio_reset;
 450         sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
 451
 452         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 453
 454         if (!pmdio->realbus) {
 455                 printf("No bus with name %s\n", realbusname);
 456                 free(bus);
 457                 free(pmdio);
 458                 return -1;
 459         }
 460
 461         pmdio->muxval = muxval;
 462         bus->priv = pmdio;
 463
 464         return mdio_register(bus);
 465 }
 466
 467 /*
 468  * Initialize the dpmac_info array.
 469  *
 470  */
 471 static void initialize_dpmac_to_slot(void)
 472 {
 473         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 474         u32 serdes1_prtcl, cfg;
 475
 476         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 477                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 478         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 479         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 480
 481         switch (serdes1_prtcl) {
 482         case 0x12:
 483                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 484                        serdes1_prtcl);
 485                 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
 486                 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
 487                 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
 488                 lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
 489                 break;
 490         case 0x15:
 491         case 0x1D:
 492                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 493                        serdes1_prtcl);
 494                 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
 495                 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
 496                 lane_to_slot_fsm1[2] = EMI_NONE;
 497                 lane_to_slot_fsm1[3] = EMI_NONE;
 498                 break;
 499         case 0x1E:
 500                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 501                        serdes1_prtcl);
 502                 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
 503                 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
 504                 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
 505                 lane_to_slot_fsm1[3] = EMI_NONE;
 506                 break;
 507         case 0x3A:
 508                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 509                        serdes1_prtcl);
 510                 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
 511                 lane_to_slot_fsm1[1] = EMI_NONE;
 512                 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
 513                 lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
 514                 break;
 515
 516         default:
 517                 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
 518                        __func__, serdes1_prtcl);
 519                 break;
 520         }
 521 }
 522
 523 void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
 524 {
 525         struct mii_dev *bus;
 526         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 527         u32 serdes1_prtcl, cfg;
 528
 529         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 530                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 531         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 532         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 533
 534         int *riser_phy_addr;
 535         char *env_hwconfig = env_get("hwconfig");
 536
 537         if (hwconfig_f("xqsgmii", env_hwconfig))
 538                 riser_phy_addr = &xqsgii_riser_phy_addr[0];
 539         else
 540                 riser_phy_addr = &sgmii_riser_phy_addr[0];
 541
 542         switch (serdes1_prtcl) {
 543         case 0x12:
 544         case 0x15:
 545         case 0x1E:
 546         case 0x3A:
 547                 switch (dpmac_id) {
 548                 case 1:
 549                         wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]);
 550                         break;
 551                 case 2:
 552                         wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]);
 553                         break;
 554                 case 3:
 555                         wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]);
 556                         break;
 557                 case 7:
 558                         wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]);
 559                         break;
 560                 default:
 561                         printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
 562                         break;
 563                 }
 564                 break;
 565         default:
 566                 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
 567                        __func__, serdes1_prtcl);
 568                 return;
 569         }
 570         dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
 571         bus = mii_dev_for_muxval(EMI1_SLOT1);
 572         wriop_set_mdio(dpmac_id, bus);
 573 }
 574
 575 void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
 576 {
 577         struct mii_dev *bus;
 578         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 579         u32 serdes1_prtcl, cfg;
 580
 581         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 582                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 583         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 584         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 585
 586         switch (serdes1_prtcl) {
 587         case 0x1D:
 588         case 0x1E:
 589                 switch (dpmac_id) {
 590                 case 3:
 591                 case 4:
 592                 case 5:
 593                 case 6:
 594                         wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9);
 595                         break;
 596                 case 7:
 597                 case 8:
 598                 case 9:
 599                 case 10:
 600                         wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1);
 601                         break;
 602                 }
 603
 604                 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
 605                 bus = mii_dev_for_muxval(EMI1_SLOT1);
 606                 wriop_set_mdio(dpmac_id, bus);
 607                 break;
 608         default:
 609                 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
 610                        serdes1_prtcl);
 611                 break;
 612         }
 613 }
 614
 615 void ls1088a_handle_phy_interface_xsgmii(int i)
 616 {
 617         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 618         u32 serdes1_prtcl, cfg;
 619
 620         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 621                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 622         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 623         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 624
 625         switch (serdes1_prtcl) {
 626         case 0x15:
 627         case 0x1D:
 628         case 0x1E:
 629                 wriop_set_phy_address(i, 0, i + 26);
 630                 ls1088a_qds_enable_SFP_TX(SFP_TX);
 631                 break;
 632         default:
 633                 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
 634                        serdes1_prtcl);
 635                 break;
 636         }
 637 }
 638
 639 static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
 640 {
 641         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 642         u32 serdes1_prtcl, cfg;
 643         struct mii_dev *bus;
 644
 645         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 646                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 647         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 648         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 649
 650         switch (dpmac_id) {
 651         case 4:
 652                 wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR);
 653                 dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
 654                 bus = mii_dev_for_muxval(EMI1_RGMII1);
 655                 wriop_set_mdio(dpmac_id, bus);
 656                 break;
 657         case 5:
 658                 wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR);
 659                 dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
 660                 bus = mii_dev_for_muxval(EMI1_RGMII2);
 661                 wriop_set_mdio(dpmac_id, bus);
 662                 break;
 663         default:
 664                 printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
 665                        serdes1_prtcl);
 666                 break;
 667         }
 668 }
 669 #endif
 670
 671 int board_eth_init(bd_t *bis)
 672 {
 673         int error = 0, i;
 674 #ifdef CONFIG_FSL_MC_ENET
 675         struct memac_mdio_info *memac_mdio0_info;
 676         char *env_hwconfig = env_get("hwconfig");
 677
 678         initialize_dpmac_to_slot();
 679
 680         memac_mdio0_info = (struct memac_mdio_info *)malloc(
 681                                         sizeof(struct memac_mdio_info));
 682         memac_mdio0_info->regs =
 683                 (struct memac_mdio_controller *)
 684                                         CONFIG_SYS_FSL_WRIOP1_MDIO1;
 685         memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
 686
 687         /* Register the real MDIO1 bus */
 688         fm_memac_mdio_init(bis, memac_mdio0_info);
 689         /* Register the muxing front-ends to the MDIO buses */
 690         ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
 691         ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
 692         ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
 693
 694         for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 695                 switch (wriop_get_enet_if(i)) {
 696                 case PHY_INTERFACE_MODE_RGMII:
 697                 case PHY_INTERFACE_MODE_RGMII_ID:
 698                         ls1088a_handle_phy_interface_rgmii(i);
 699                         break;
 700                 case PHY_INTERFACE_MODE_QSGMII:
 701                         ls1088a_handle_phy_interface_qsgmii(i);
 702                         break;
 703                 case PHY_INTERFACE_MODE_SGMII:
 704                         ls1088a_handle_phy_interface_sgmii(i);
 705                         break;
 706                 case PHY_INTERFACE_MODE_XGMII:
 707                         ls1088a_handle_phy_interface_xsgmii(i);
 708                         break;
 709                 default:
 710                         break;
 711
 712                 if (i == 16)
 713                         i = NUM_WRIOP_PORTS;
 714                 }
 715         }
 716
 717         error = cpu_eth_init(bis);
 718
 719         if (hwconfig_f("xqsgmii", env_hwconfig)) {
 720                 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 721                         switch (wriop_get_enet_if(i)) {
 722                         case PHY_INTERFACE_MODE_QSGMII:
 723                                 qsgmii_configure_repeater(i);
 724                                 break;
 725                         case PHY_INTERFACE_MODE_SGMII:
 726                                 sgmii_configure_repeater(i);
 727                                 break;
 728                         default:
 729                                 break;
 730                         }
 731
 732                         if (i == 16)
 733                                 i = NUM_WRIOP_PORTS;
 734                 }
 735         }
 736 #endif
 737         error = pci_eth_init(bis);
 738         return error;
 739 }
 740
 741 #if defined(CONFIG_RESET_PHY_R)
 742 void reset_phy(void)
 743 {
 744         mc_env_boot();
 745 }
 746 #endif /* CONFIG_RESET_PHY_R */