board/freescale/ls1088a/eth_ls1088aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <env.h>
   9 #include <net.h>
  10 #include <netdev.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <hwconfig.h>
  14 #include <fsl_mdio.h>
  15 #include <malloc.h>
  16 #include <phy.h>
  17 #include <fm_eth.h>
  18 #include <i2c.h>
  19 #include <miiphy.h>
  20 #include <fsl-mc/fsl_mc.h>
  21 #include <fsl-mc/ldpaa_wriop.h>
  22
  23 #include "../common/qixis.h"
  24
  25 #include "ls1088a_qixis.h"
  26
  27 #ifndef CONFIG_DM_ETH
  28 #ifdef CONFIG_FSL_MC_ENET
  29
  30 #define SFP_TX          0
  31
  32  /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  33  *   Bank 1 -> Lanes A, B, C, D,
  34  *   Bank 2 -> Lanes A,B, C, D,
  35  */
  36
  37  /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
  38   * means that the mapping must be determined dynamically, or that the lane
  39   * maps to something other than a board slot.
  40   */
  41
  42 static u8 lane_to_slot_fsm1[] = {
  43         0, 0, 0, 0, 0, 0, 0, 0
  44 };
  45
  46 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  47  * housed.
  48  */
  49
  50 static int xqsgii_riser_phy_addr[] = {
  51         XQSGMII_CARD_PHY1_PORT0_ADDR,
  52         XQSGMII_CARD_PHY2_PORT0_ADDR,
  53         XQSGMII_CARD_PHY3_PORT0_ADDR,
  54         XQSGMII_CARD_PHY4_PORT0_ADDR,
  55         XQSGMII_CARD_PHY3_PORT2_ADDR,
  56         XQSGMII_CARD_PHY1_PORT2_ADDR,
  57         XQSGMII_CARD_PHY4_PORT2_ADDR,
  58         XQSGMII_CARD_PHY2_PORT2_ADDR,
  59 };
  60
  61 static int sgmii_riser_phy_addr[] = {
  62         SGMII_CARD_PORT1_PHY_ADDR,
  63         SGMII_CARD_PORT2_PHY_ADDR,
  64         SGMII_CARD_PORT3_PHY_ADDR,
  65         SGMII_CARD_PORT4_PHY_ADDR,
  66 };
  67
  68 /* Slot2 does not have EMI connections */
  69 #define EMI_NONE        0xFF
  70 #define EMI1_RGMII1     0
  71 #define EMI1_RGMII2     1
  72 #define EMI1_SLOT1      2
  73
  74 static const char * const mdio_names[] = {
  75         "LS1088A_QDS_MDIO0",
  76         "LS1088A_QDS_MDIO1",
  77         "LS1088A_QDS_MDIO2",
  78         DEFAULT_WRIOP_MDIO2_NAME,
  79 };
  80
  81 struct ls1088a_qds_mdio {
  82         u8 muxval;
  83         struct mii_dev *realbus;
  84 };
  85
  86 struct reg_pair {
  87         uint addr;
  88         u8 *val;
  89 };
  90
  91 static void sgmii_configure_repeater(int dpmac)
  92 {
  93         struct mii_dev *bus;
  94         uint8_t a = 0xf;
  95         int i, j, k, ret;
  96         unsigned short value;
  97         const char *dev = "LS1088A_QDS_MDIO2";
  98         int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
  99         int i2c_phy_addr = 0;
 100         int phy_addr = 0;
 101
 102         uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
 103         uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 104         uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 105         uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 106
 107         u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
 108         struct reg_pair reg_pair[10] = {
 109                 {6, &reg_val[0]}, {4, &reg_val[1]},
 110                 {8, &reg_val[2]}, {0xf, NULL},
 111                 {0x11, NULL}, {0x16, NULL},
 112                 {0x18, NULL}, {0x23, &reg_val[3]},
 113                 {0x2d, &reg_val[4]}, {4, &reg_val[5]},
 114         };
 115 #ifdef CONFIG_DM_I2C
 116         struct udevice *udev;
 117 #endif
 118
 119         /* Set I2c to Slot 1 */
 120 #ifndef CONFIG_DM_I2C
 121         ret = i2c_write(0x77, 0, 0, &a, 1);
 122 #else
 123         ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
 124         if (!ret)
 125                 ret = dm_i2c_write(udev, 0, &a, 1);
 126 #endif
 127         if (ret)
 128                 goto error;
 129
 130         switch (dpmac) {
 131         case 1:
 132                 i2c_phy_addr = i2c_addr[1];
 133                 phy_addr = 4;
 134                 break;
 135         case 2:
 136                 i2c_phy_addr = i2c_addr[0];
 137                 phy_addr = 0;
 138                 break;
 139         case 3:
 140                 i2c_phy_addr = i2c_addr[3];
 141                 phy_addr = 0xc;
 142                 break;
 143         case 7:
 144                 i2c_phy_addr = i2c_addr[2];
 145                 phy_addr = 8;
 146                 break;
 147         }
 148
 149         /* Check the PHY status */
 150         ret = miiphy_set_current_dev(dev);
 151         if (ret > 0)
 152                 goto error;
 153
 154         bus = mdio_get_current_dev();
 155         debug("Reading from bus %s\n", bus->name);
 156
 157         ret = miiphy_write(dev, phy_addr, 0x1f, 3);
 158         if (ret > 0)
 159                 goto error;
 160
 161         mdelay(10);
 162         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 163         if (ret > 0)
 164                         goto error;
 165
 166         mdelay(10);
 167
 168         if ((value & 0xfff) == 0x401) {
 169                 miiphy_write(dev, phy_addr, 0x1f, 0);
 170                 printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
 171                 return;
 172         }
 173
 174 #ifdef CONFIG_DM_I2C
 175         i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
 176 #endif
 177
 178         for (i = 0; i < 4; i++) {
 179                 for (j = 0; j < 4; j++) {
 180                         reg_pair[3].val = &ch_a_eq[i];
 181                         reg_pair[4].val = &ch_a_ctl2[j];
 182                         reg_pair[5].val = &ch_b_eq[i];
 183                         reg_pair[6].val = &ch_b_ctl2[j];
 184                         for (k = 0; k < 10; k++) {
 185 #ifndef CONFIG_DM_I2C
 186                                 ret = i2c_write(i2c_phy_addr,
 187                                                 reg_pair[k].addr,
 188                                                 1, reg_pair[k].val, 1);
 189 #else
 190                                 ret = i2c_get_chip_for_busnum(0,
 191                                                               i2c_phy_addr,
 192                                                               1, &udev);
 193                                 if (!ret)
 194                                         ret = dm_i2c_write(udev,
 195                                                            reg_pair[k].addr,
 196                                                            reg_pair[k].val, 1);
 197 #endif
 198                                 if (ret)
 199                                         goto error;
 200                         }
 201
 202                         mdelay(100);
 203                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 204                         if (ret > 0)
 205                                 goto error;
 206
 207                         mdelay(100);
 208                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 209                         if (ret > 0)
 210                                 goto error;
 211
 212                         if ((value & 0xfff) == 0x401) {
 213                                 printf("DPMAC %d :PHY is configured ",
 214                                        dpmac);
 215                                 printf("after setting repeater 0x%x\n",
 216                                        value);
 217                                 i = 5;
 218                                 j = 5;
 219                         } else {
 220                                 printf("DPMAC %d :PHY is failed to ",
 221                                        dpmac);
 222                                 printf("configure the repeater 0x%x\n", value);
 223                         }
 224                 }
 225         }
 226         miiphy_write(dev, phy_addr, 0x1f, 0);
 227 error:
 228         if (ret)
 229                 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
 230         return;
 231 }
 232
 233 static void qsgmii_configure_repeater(int dpmac)
 234 {
 235         uint8_t a = 0xf;
 236         int i, j, k;
 237         int i2c_phy_addr = 0;
 238         int phy_addr = 0;
 239         int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
 240
 241         uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
 242         uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 243         uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 244         uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 245
 246         u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
 247         struct reg_pair reg_pair[10] = {
 248                 {6, &reg_val[0]}, {4, &reg_val[1]},
 249                 {8, &reg_val[2]}, {0xf, NULL},
 250                 {0x11, NULL}, {0x16, NULL},
 251                 {0x18, NULL}, {0x23, &reg_val[3]},
 252                 {0x2d, &reg_val[4]}, {4, &reg_val[5]},
 253         };
 254
 255         const char *dev = mdio_names[EMI1_SLOT1];
 256         int ret = 0;
 257         unsigned short value;
 258 #ifdef CONFIG_DM_I2C
 259         struct udevice *udev;
 260 #endif
 261
 262         /* Set I2c to Slot 1 */
 263 #ifndef CONFIG_DM_I2C
 264         ret = i2c_write(0x77, 0, 0, &a, 1);
 265 #else
 266         ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
 267         if (!ret)
 268                 ret = dm_i2c_write(udev, 0, &a, 1);
 269 #endif
 270         if (ret)
 271                 goto error;
 272
 273         switch (dpmac) {
 274         case 7:
 275         case 8:
 276         case 9:
 277         case 10:
 278                 i2c_phy_addr = i2c_addr[2];
 279                 phy_addr = 8;
 280                 break;
 281
 282         case 3:
 283         case 4:
 284         case 5:
 285         case 6:
 286                 i2c_phy_addr = i2c_addr[3];
 287                 phy_addr = 0xc;
 288                 break;
 289         }
 290
 291         /* Check the PHY status */
 292         ret = miiphy_set_current_dev(dev);
 293         ret = miiphy_write(dev, phy_addr, 0x1f, 3);
 294         mdelay(10);
 295         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 296         mdelay(10);
 297         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 298         mdelay(10);
 299         if ((value & 0xf) == 0xf) {
 300                 miiphy_write(dev, phy_addr, 0x1f, 0);
 301                 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
 302                 return;
 303         }
 304
 305 #ifdef CONFIG_DM_I2C
 306         i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
 307 #endif
 308
 309         for (i = 0; i < 4; i++) {
 310                 for (j = 0; j < 4; j++) {
 311                         reg_pair[3].val = &ch_a_eq[i];
 312                         reg_pair[4].val = &ch_a_ctl2[j];
 313                         reg_pair[5].val = &ch_b_eq[i];
 314                         reg_pair[6].val = &ch_b_ctl2[j];
 315
 316                         for (k = 0; k < 10; k++) {
 317 #ifndef CONFIG_DM_I2C
 318                                 ret = i2c_write(i2c_phy_addr,
 319                                                 reg_pair[k].addr,
 320                                                 1, reg_pair[k].val, 1);
 321 #else
 322                                 ret = i2c_get_chip_for_busnum(0,
 323                                                               i2c_addr[dpmac],
 324                                                               1, &udev);
 325                                 if (!ret)
 326                                         ret = dm_i2c_write(udev,
 327                                                            reg_pair[k].addr,
 328                                                            reg_pair[k].val, 1);
 329 #endif
 330                                 if (ret)
 331                                         goto error;
 332                         }
 333
 334                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 335                         if (ret > 0)
 336                                 goto error;
 337                         mdelay(1);
 338                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 339                         if (ret > 0)
 340                                 goto error;
 341                         mdelay(10);
 342                         if ((value & 0xf) == 0xf) {
 343                                 miiphy_write(dev, phy_addr, 0x1f, 0);
 344                                 printf("DPMAC %d :PHY is ..... Configured\n",
 345                                        dpmac);
 346                                 return;
 347                         }
 348                 }
 349         }
 350 error:
 351         printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
 352         return;
 353 }
 354
 355 static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
 356 {
 357         return mdio_names[muxval];
 358 }
 359
 360 struct mii_dev *mii_dev_for_muxval(u8 muxval)
 361 {
 362         struct mii_dev *bus;
 363         const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
 364
 365         if (!name) {
 366                 printf("No bus for muxval %x\n", muxval);
 367                 return NULL;
 368         }
 369
 370         bus = miiphy_get_dev_by_name(name);
 371
 372         if (!bus) {
 373                 printf("No bus by name %s\n", name);
 374                 return NULL;
 375         }
 376
 377         return bus;
 378 }
 379
 380 static void ls1088a_qds_enable_SFP_TX(u8 muxval)
 381 {
 382         u8 brdcfg9;
 383
 384         brdcfg9 = QIXIS_READ(brdcfg[9]);
 385         brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
 386         brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
 387         QIXIS_WRITE(brdcfg[9], brdcfg9);
 388 }
 389
 390 static void ls1088a_qds_mux_mdio(u8 muxval)
 391 {
 392         u8 brdcfg4;
 393
 394         if (muxval <= 5) {
 395                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 396                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 397                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 398                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 399         }
 400 }
 401
 402 static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
 403                                  int devad, int regnum)
 404 {
 405         struct ls1088a_qds_mdio *priv = bus->priv;
 406
 407         ls1088a_qds_mux_mdio(priv->muxval);
 408
 409         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 410 }
 411
 412 static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 413                                   int regnum, u16 value)
 414 {
 415         struct ls1088a_qds_mdio *priv = bus->priv;
 416
 417         ls1088a_qds_mux_mdio(priv->muxval);
 418
 419         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 420 }
 421
 422 static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
 423 {
 424         struct ls1088a_qds_mdio *priv = bus->priv;
 425
 426         return priv->realbus->reset(priv->realbus);
 427 }
 428
 429 static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
 430 {
 431         struct ls1088a_qds_mdio *pmdio;
 432         struct mii_dev *bus = mdio_alloc();
 433
 434         if (!bus) {
 435                 printf("Failed to allocate ls1088a_qds MDIO bus\n");
 436                 return -1;
 437         }
 438
 439         pmdio = malloc(sizeof(*pmdio));
 440         if (!pmdio) {
 441                 printf("Failed to allocate ls1088a_qds private data\n");
 442                 free(bus);
 443                 return -1;
 444         }
 445
 446         bus->read = ls1088a_qds_mdio_read;
 447         bus->write = ls1088a_qds_mdio_write;
 448         bus->reset = ls1088a_qds_mdio_reset;
 449         sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
 450
 451         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 452
 453         if (!pmdio->realbus) {
 454                 printf("No bus with name %s\n", realbusname);
 455                 free(bus);
 456                 free(pmdio);
 457                 return -1;
 458         }
 459
 460         pmdio->muxval = muxval;
 461         bus->priv = pmdio;
 462
 463         return mdio_register(bus);
 464 }
 465
 466 /*
 467  * Initialize the dpmac_info array.
 468  *
 469  */
 470 static void initialize_dpmac_to_slot(void)
 471 {
 472         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 473         u32 serdes1_prtcl, cfg;
 474
 475         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 476                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 477         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 478         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 479
 480         switch (serdes1_prtcl) {
 481         case 0x12:
 482                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 483                        serdes1_prtcl);
 484                 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
 485                 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
 486                 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
 487                 lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
 488                 break;
 489         case 0x15:
 490         case 0x1D:
 491                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 492                        serdes1_prtcl);
 493                 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
 494                 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
 495                 lane_to_slot_fsm1[2] = EMI_NONE;
 496                 lane_to_slot_fsm1[3] = EMI_NONE;
 497                 break;
 498         case 0x1E:
 499                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 500                        serdes1_prtcl);
 501                 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
 502                 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
 503                 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
 504                 lane_to_slot_fsm1[3] = EMI_NONE;
 505                 break;
 506         case 0x3A:
 507                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 508                        serdes1_prtcl);
 509                 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
 510                 lane_to_slot_fsm1[1] = EMI_NONE;
 511                 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
 512                 lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
 513                 break;
 514
 515         default:
 516                 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
 517                        __func__, serdes1_prtcl);
 518                 break;
 519         }
 520 }
 521
 522 void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
 523 {
 524         struct mii_dev *bus;
 525         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 526         u32 serdes1_prtcl, cfg;
 527
 528         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 529                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 530         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 531         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 532
 533         int *riser_phy_addr;
 534         char *env_hwconfig = env_get("hwconfig");
 535
 536         if (hwconfig_f("xqsgmii", env_hwconfig))
 537                 riser_phy_addr = &xqsgii_riser_phy_addr[0];
 538         else
 539                 riser_phy_addr = &sgmii_riser_phy_addr[0];
 540
 541         switch (serdes1_prtcl) {
 542         case 0x12:
 543         case 0x15:
 544         case 0x1E:
 545         case 0x3A:
 546                 switch (dpmac_id) {
 547                 case 1:
 548                         wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]);
 549                         break;
 550                 case 2:
 551                         wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]);
 552                         break;
 553                 case 3:
 554                         wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]);
 555                         break;
 556                 case 7:
 557                         wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]);
 558                         break;
 559                 default:
 560                         printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
 561                         break;
 562                 }
 563                 break;
 564         default:
 565                 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
 566                        __func__, serdes1_prtcl);
 567                 return;
 568         }
 569         dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
 570         bus = mii_dev_for_muxval(EMI1_SLOT1);
 571         wriop_set_mdio(dpmac_id, bus);
 572 }
 573
 574 void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
 575 {
 576         struct mii_dev *bus;
 577         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 578         u32 serdes1_prtcl, cfg;
 579
 580         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 581                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 582         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 583         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 584
 585         switch (serdes1_prtcl) {
 586         case 0x1D:
 587         case 0x1E:
 588                 switch (dpmac_id) {
 589                 case 3:
 590                 case 4:
 591                 case 5:
 592                 case 6:
 593                         wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9);
 594                         break;
 595                 case 7:
 596                 case 8:
 597                 case 9:
 598                 case 10:
 599                         wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1);
 600                         break;
 601                 }
 602
 603                 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
 604                 bus = mii_dev_for_muxval(EMI1_SLOT1);
 605                 wriop_set_mdio(dpmac_id, bus);
 606                 break;
 607         default:
 608                 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
 609                        serdes1_prtcl);
 610                 break;
 611         }
 612 }
 613
 614 void ls1088a_handle_phy_interface_xsgmii(int i)
 615 {
 616         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 617         u32 serdes1_prtcl, cfg;
 618
 619         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 620                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 621         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 622         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 623
 624         switch (serdes1_prtcl) {
 625         case 0x15:
 626         case 0x1D:
 627         case 0x1E:
 628                 wriop_set_phy_address(i, 0, i + 26);
 629                 ls1088a_qds_enable_SFP_TX(SFP_TX);
 630                 break;
 631         default:
 632                 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
 633                        serdes1_prtcl);
 634                 break;
 635         }
 636 }
 637
 638 static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
 639 {
 640         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 641         u32 serdes1_prtcl, cfg;
 642         struct mii_dev *bus;
 643
 644         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 645                                 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 646         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 647         serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
 648
 649         switch (dpmac_id) {
 650         case 4:
 651                 wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR);
 652                 dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
 653                 bus = mii_dev_for_muxval(EMI1_RGMII1);
 654                 wriop_set_mdio(dpmac_id, bus);
 655                 break;
 656         case 5:
 657                 wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR);
 658                 dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
 659                 bus = mii_dev_for_muxval(EMI1_RGMII2);
 660                 wriop_set_mdio(dpmac_id, bus);
 661                 break;
 662         default:
 663                 printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
 664                        serdes1_prtcl);
 665                 break;
 666         }
 667 }
 668 #endif
 669
 670 int board_eth_init(bd_t *bis)
 671 {
 672         int error = 0, i;
 673 #ifdef CONFIG_FSL_MC_ENET
 674         struct memac_mdio_info *memac_mdio0_info;
 675         char *env_hwconfig = env_get("hwconfig");
 676
 677         initialize_dpmac_to_slot();
 678
 679         memac_mdio0_info = (struct memac_mdio_info *)malloc(
 680                                         sizeof(struct memac_mdio_info));
 681         memac_mdio0_info->regs =
 682                 (struct memac_mdio_controller *)
 683                                         CONFIG_SYS_FSL_WRIOP1_MDIO1;
 684         memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
 685
 686         /* Register the real MDIO1 bus */
 687         fm_memac_mdio_init(bis, memac_mdio0_info);
 688         /* Register the muxing front-ends to the MDIO buses */
 689         ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
 690         ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
 691         ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
 692
 693         for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 694                 switch (wriop_get_enet_if(i)) {
 695                 case PHY_INTERFACE_MODE_RGMII:
 696                 case PHY_INTERFACE_MODE_RGMII_ID:
 697                         ls1088a_handle_phy_interface_rgmii(i);
 698                         break;
 699                 case PHY_INTERFACE_MODE_QSGMII:
 700                         ls1088a_handle_phy_interface_qsgmii(i);
 701                         break;
 702                 case PHY_INTERFACE_MODE_SGMII:
 703                         ls1088a_handle_phy_interface_sgmii(i);
 704                         break;
 705                 case PHY_INTERFACE_MODE_XGMII:
 706                         ls1088a_handle_phy_interface_xsgmii(i);
 707                         break;
 708                 default:
 709                         break;
 710
 711                 if (i == 16)
 712                         i = NUM_WRIOP_PORTS;
 713                 }
 714         }
 715
 716         error = cpu_eth_init(bis);
 717
 718         if (hwconfig_f("xqsgmii", env_hwconfig)) {
 719                 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 720                         switch (wriop_get_enet_if(i)) {
 721                         case PHY_INTERFACE_MODE_QSGMII:
 722                                 qsgmii_configure_repeater(i);
 723                                 break;
 724                         case PHY_INTERFACE_MODE_SGMII:
 725                                 sgmii_configure_repeater(i);
 726                                 break;
 727                         default:
 728                                 break;
 729                         }
 730
 731                         if (i == 16)
 732                                 i = NUM_WRIOP_PORTS;
 733                 }
 734         }
 735 #endif
 736         error = pci_eth_init(bis);
 737         return error;
 738 }
 739 #endif // !CONFIG_DM_ETH
 740
 741 #if defined(CONFIG_RESET_PHY_R)
 742 void reset_phy(void)
 743 {
 744         mc_env_boot();
 745 }
 746 #endif /* CONFIG_RESET_PHY_R */
 747
 748 #if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
 749
 750 /* Structure to hold SERDES protocols supported in case of
 751  * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
 752  *
 753  * @serdes_block: the index of the SERDES block
 754  * @serdes_protocol: the decimal value of the protocol supported
 755  * @dts_needed: DTS notes describing the current configuration are needed
 756  *
 757  * When dts_needed is true, the board_fit_config_name_match() function
 758  * will try to exactly match the current configuration of the block with a DTS
 759  * name provided.
 760  */
 761 static struct serdes_configuration {
 762         u8 serdes_block;
 763         u32 serdes_protocol;
 764         bool dts_needed;
 765 } supported_protocols[] = {
 766         /* Serdes block #1 */
 767         {1, 21, true},
 768         {1, 29, true},
 769 };
 770
 771 #define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
 772
 773 static bool protocol_supported(u8 serdes_block, u32 protocol)
 774 {
 775         struct serdes_configuration serdes_conf;
 776         int i;
 777
 778         for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
 779                 serdes_conf = supported_protocols[i];
 780                 if (serdes_conf.serdes_block == serdes_block &&
 781                     serdes_conf.serdes_protocol == protocol)
 782                         return true;
 783         }
 784
 785         return false;
 786 }
 787
 788 static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
 789 {
 790         struct serdes_configuration serdes_conf;
 791         int i;
 792
 793         for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
 794                 serdes_conf = supported_protocols[i];
 795                 if (serdes_conf.serdes_block == serdes_block &&
 796                     serdes_conf.serdes_protocol == protocol) {
 797                         if (serdes_conf.dts_needed == true)
 798                                 sprintf(str, "%u", protocol);
 799                         else
 800                                 sprintf(str, "x");
 801                         return;
 802                 }
 803         }
 804 }
 805
 806 int board_fit_config_name_match(const char *name)
 807 {
 808         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 809         char expected_dts[100];
 810         char srds_s1_str[2];
 811         u32 srds_s1, cfg;
 812
 813         cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
 814                       FSL_CHASSIS3_SRDS1_PRTCL_MASK;
 815         cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 816         srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
 817
 818         /* Check for supported protocols. The default DTS will be used
 819          * in this case
 820          */
 821         if (!protocol_supported(1, srds_s1))
 822                 return -1;
 823
 824         get_str_protocol(1, srds_s1, srds_s1_str);
 825
 826         sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str);
 827
 828         if (!strcmp(name, expected_dts))
 829                 return 0;
 830
 831         return -1;
 832 }
 833 #endif