board/freescale/ls1043aqds/eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <net.h>
   9 #include <asm/io.h>
  10 #include <netdev.h>
  11 #include <fdt_support.h>
  12 #include <fm_eth.h>
  13 #include <fsl_mdio.h>
  14 #include <fsl_dtsec.h>
  15 #include <linux/libfdt.h>
  16 #include <malloc.h>
  17 #include <asm/arch/fsl_serdes.h>
  18
  19 #include "../common/qixis.h"
  20 #include "../common/fman.h"
  21 #include "ls1043aqds_qixis.h"
  22
  23 #define EMI_NONE        0xFF
  24 #define EMI1_RGMII1     0
  25 #define EMI1_RGMII2     1
  26 #define EMI1_SLOT1      2
  27 #define EMI1_SLOT2      3
  28 #define EMI1_SLOT3      4
  29 #define EMI1_SLOT4      5
  30 #define EMI2            6
  31
  32 static int mdio_mux[NUM_FM_PORTS];
  33
  34 static const char * const mdio_names[] = {
  35         "LS1043AQDS_MDIO_RGMII1",
  36         "LS1043AQDS_MDIO_RGMII2",
  37         "LS1043AQDS_MDIO_SLOT1",
  38         "LS1043AQDS_MDIO_SLOT2",
  39         "LS1043AQDS_MDIO_SLOT3",
  40         "LS1043AQDS_MDIO_SLOT4",
  41         "NULL",
  42 };
  43
  44 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
  45 static u8 lane_to_slot[] = {1, 2, 3, 4};
  46
  47 static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
  48 {
  49         return mdio_names[muxval];
  50 }
  51
  52 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  53 {
  54         struct mii_dev *bus;
  55         const char *name;
  56
  57         if (muxval > EMI2)
  58                 return NULL;
  59
  60         name = ls1043aqds_mdio_name_for_muxval(muxval);
  61
  62         if (!name) {
  63                 printf("No bus for muxval %x\n", muxval);
  64                 return NULL;
  65         }
  66
  67         bus = miiphy_get_dev_by_name(name);
  68
  69         if (!bus) {
  70                 printf("No bus by name %s\n", name);
  71                 return NULL;
  72         }
  73
  74         return bus;
  75 }
  76
  77 struct ls1043aqds_mdio {
  78         u8 muxval;
  79         struct mii_dev *realbus;
  80 };
  81
  82 static void ls1043aqds_mux_mdio(u8 muxval)
  83 {
  84         u8 brdcfg4;
  85
  86         if (muxval < 7) {
  87                 brdcfg4 = QIXIS_READ(brdcfg[4]);
  88                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  89                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  90                 QIXIS_WRITE(brdcfg[4], brdcfg4);
  91         }
  92 }
  93
  94 static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  95                               int regnum)
  96 {
  97         struct ls1043aqds_mdio *priv = bus->priv;
  98
  99         ls1043aqds_mux_mdio(priv->muxval);
 100
 101         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 102 }
 103
 104 static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
 105                                int regnum, u16 value)
 106 {
 107         struct ls1043aqds_mdio *priv = bus->priv;
 108
 109         ls1043aqds_mux_mdio(priv->muxval);
 110
 111         return priv->realbus->write(priv->realbus, addr, devad,
 112                                     regnum, value);
 113 }
 114
 115 static int ls1043aqds_mdio_reset(struct mii_dev *bus)
 116 {
 117         struct ls1043aqds_mdio *priv = bus->priv;
 118
 119         return priv->realbus->reset(priv->realbus);
 120 }
 121
 122 static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
 123 {
 124         struct ls1043aqds_mdio *pmdio;
 125         struct mii_dev *bus = mdio_alloc();
 126
 127         if (!bus) {
 128                 printf("Failed to allocate ls1043aqds MDIO bus\n");
 129                 return -1;
 130         }
 131
 132         pmdio = malloc(sizeof(*pmdio));
 133         if (!pmdio) {
 134                 printf("Failed to allocate ls1043aqds private data\n");
 135                 free(bus);
 136                 return -1;
 137         }
 138
 139         bus->read = ls1043aqds_mdio_read;
 140         bus->write = ls1043aqds_mdio_write;
 141         bus->reset = ls1043aqds_mdio_reset;
 142         strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
 143
 144         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 145
 146         if (!pmdio->realbus) {
 147                 printf("No bus with name %s\n", realbusname);
 148                 free(bus);
 149                 free(pmdio);
 150                 return -1;
 151         }
 152
 153         pmdio->muxval = muxval;
 154         bus->priv = pmdio;
 155         return mdio_register(bus);
 156 }
 157
 158 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 159                               enum fm_port port, int offset)
 160 {
 161         struct fixed_link f_link;
 162
 163         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 164                 if (port == FM1_DTSEC9) {
 165                         fdt_set_phy_handle(fdt, compat, addr,
 166                                            "sgmii-riser-s1-p1");
 167                 } else if (port == FM1_DTSEC2) {
 168                         fdt_set_phy_handle(fdt, compat, addr,
 169                                            "sgmii-riser-s2-p1");
 170                 } else if (port == FM1_DTSEC5) {
 171                         fdt_set_phy_handle(fdt, compat, addr,
 172                                            "sgmii-riser-s3-p1");
 173                 } else if (port == FM1_DTSEC6) {
 174                         fdt_set_phy_handle(fdt, compat, addr,
 175                                            "sgmii-riser-s4-p1");
 176                 }
 177         } else if (fm_info_get_enet_if(port) ==
 178                    PHY_INTERFACE_MODE_SGMII_2500) {
 179                 /* 2.5G SGMII interface */
 180                 f_link.phy_id = cpu_to_fdt32(port);
 181                 f_link.duplex = cpu_to_fdt32(1);
 182                 f_link.link_speed = cpu_to_fdt32(1000);
 183                 f_link.pause = 0;
 184                 f_link.asym_pause = 0;
 185                 /* no PHY for 2.5G SGMII */
 186                 fdt_delprop(fdt, offset, "phy-handle");
 187                 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
 188                 fdt_setprop_string(fdt, offset, "phy-connection-type",
 189                                    "sgmii-2500");
 190         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
 191                 switch (mdio_mux[port]) {
 192                 case EMI1_SLOT1:
 193                         switch (port) {
 194                         case FM1_DTSEC1:
 195                                 fdt_set_phy_handle(fdt, compat, addr,
 196                                                    "qsgmii-s1-p1");
 197                                 break;
 198                         case FM1_DTSEC2:
 199                                 fdt_set_phy_handle(fdt, compat, addr,
 200                                                    "qsgmii-s1-p2");
 201                                 break;
 202                         case FM1_DTSEC5:
 203                                 fdt_set_phy_handle(fdt, compat, addr,
 204                                                    "qsgmii-s1-p3");
 205                                 break;
 206                         case FM1_DTSEC6:
 207                                 fdt_set_phy_handle(fdt, compat, addr,
 208                                                    "qsgmii-s1-p4");
 209                                 break;
 210                         default:
 211                                 break;
 212                         }
 213                         break;
 214                 case EMI1_SLOT2:
 215                         switch (port) {
 216                         case FM1_DTSEC1:
 217                                 fdt_set_phy_handle(fdt, compat, addr,
 218                                                    "qsgmii-s2-p1");
 219                                 break;
 220                         case FM1_DTSEC2:
 221                                 fdt_set_phy_handle(fdt, compat, addr,
 222                                                    "qsgmii-s2-p2");
 223                                 break;
 224                         case FM1_DTSEC5:
 225                                 fdt_set_phy_handle(fdt, compat, addr,
 226                                                    "qsgmii-s2-p3");
 227                                 break;
 228                         case FM1_DTSEC6:
 229                                 fdt_set_phy_handle(fdt, compat, addr,
 230                                                    "qsgmii-s2-p4");
 231                                 break;
 232                         default:
 233                                 break;
 234                         }
 235                         break;
 236                 default:
 237                         break;
 238                 }
 239                 fdt_delprop(fdt, offset, "phy-connection-type");
 240                 fdt_setprop_string(fdt, offset, "phy-connection-type",
 241                                    "qsgmii");
 242         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
 243                    port == FM1_10GEC1) {
 244                 /* XFI interface */
 245                 f_link.phy_id = cpu_to_fdt32(port);
 246                 f_link.duplex = cpu_to_fdt32(1);
 247                 f_link.link_speed = cpu_to_fdt32(10000);
 248                 f_link.pause = 0;
 249                 f_link.asym_pause = 0;
 250                 /* no PHY for XFI */
 251                 fdt_delprop(fdt, offset, "phy-handle");
 252                 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
 253                 fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
 254         }
 255 }
 256
 257 void fdt_fixup_board_enet(void *fdt)
 258 {
 259         int i;
 260         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 261         u32 srds_s1;
 262
 263         srds_s1 = in_be32(&gur->rcwsr[4]) &
 264                         FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
 265         srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 266
 267         for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 268                 switch (fm_info_get_enet_if(i)) {
 269                 case PHY_INTERFACE_MODE_SGMII:
 270                 case PHY_INTERFACE_MODE_QSGMII:
 271                         switch (mdio_mux[i]) {
 272                         case EMI1_SLOT1:
 273                                 fdt_status_okay_by_alias(fdt, "emi1-slot1");
 274                                 break;
 275                         case EMI1_SLOT2:
 276                                 fdt_status_okay_by_alias(fdt, "emi1-slot2");
 277                                 break;
 278                         case EMI1_SLOT3:
 279                                 fdt_status_okay_by_alias(fdt, "emi1-slot3");
 280                                 break;
 281                         case EMI1_SLOT4:
 282                                 fdt_status_okay_by_alias(fdt, "emi1-slot4");
 283                                 break;
 284                         default:
 285                                 break;
 286                         }
 287                         break;
 288                 case PHY_INTERFACE_MODE_XGMII:
 289                         break;
 290                 default:
 291                         break;
 292                 }
 293         }
 294 }
 295
 296 int board_eth_init(bd_t *bis)
 297 {
 298 #ifdef CONFIG_FMAN_ENET
 299         int i, idx, lane, slot, interface;
 300         struct memac_mdio_info dtsec_mdio_info;
 301         struct memac_mdio_info tgec_mdio_info;
 302         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 303         u32 srds_s1;
 304
 305         srds_s1 = in_be32(&gur->rcwsr[4]) &
 306                         FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
 307         srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 308
 309         /* Initialize the mdio_mux array so we can recognize empty elements */
 310         for (i = 0; i < NUM_FM_PORTS; i++)
 311                 mdio_mux[i] = EMI_NONE;
 312
 313         dtsec_mdio_info.regs =
 314                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
 315
 316         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 317
 318         /* Register the 1G MDIO bus */
 319         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 320
 321         tgec_mdio_info.regs =
 322                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
 323         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 324
 325         /* Register the 10G MDIO bus */
 326         fm_memac_mdio_init(bis, &tgec_mdio_info);
 327
 328         /* Register the muxing front-ends to the MDIO buses */
 329         ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
 330         ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
 331         ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 332         ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 333         ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 334         ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 335         ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 336
 337         /* Set the two on-board RGMII PHY address */
 338         fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
 339         fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
 340
 341         switch (srds_s1) {
 342         case 0x2555:
 343                 /* 2.5G SGMII on lane A, MAC 9 */
 344                 fm_info_set_phy_address(FM1_DTSEC9, 9);
 345                 break;
 346         case 0x4555:
 347         case 0x4558:
 348                 /* QSGMII on lane A, MAC 1/2/5/6 */
 349                 fm_info_set_phy_address(FM1_DTSEC1,
 350                                         QSGMII_CARD_PORT1_PHY_ADDR_S1);
 351                 fm_info_set_phy_address(FM1_DTSEC2,
 352                                         QSGMII_CARD_PORT2_PHY_ADDR_S1);
 353                 fm_info_set_phy_address(FM1_DTSEC5,
 354                                         QSGMII_CARD_PORT3_PHY_ADDR_S1);
 355                 fm_info_set_phy_address(FM1_DTSEC6,
 356                                         QSGMII_CARD_PORT4_PHY_ADDR_S1);
 357                 break;
 358         case 0x1355:
 359                 /* SGMII on lane B, MAC 2*/
 360                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 361                 break;
 362         case 0x2355:
 363                 /* 2.5G SGMII on lane A, MAC 9 */
 364                 fm_info_set_phy_address(FM1_DTSEC9, 9);
 365                 /* SGMII on lane B, MAC 2*/
 366                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 367                 break;
 368         case 0x3335:
 369                 /* SGMII on lane C, MAC 5 */
 370                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
 371         case 0x3355:
 372         case 0x3358:
 373                 /* SGMII on lane B, MAC 2 */
 374                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 375         case 0x3555:
 376         case 0x3558:
 377                 /* SGMII on lane A, MAC 9 */
 378                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 379                 break;
 380         case 0x1455:
 381                 /* QSGMII on lane B, MAC 1/2/5/6 */
 382                 fm_info_set_phy_address(FM1_DTSEC1,
 383                                         QSGMII_CARD_PORT1_PHY_ADDR_S2);
 384                 fm_info_set_phy_address(FM1_DTSEC2,
 385                                         QSGMII_CARD_PORT2_PHY_ADDR_S2);
 386                 fm_info_set_phy_address(FM1_DTSEC5,
 387                                         QSGMII_CARD_PORT3_PHY_ADDR_S2);
 388                 fm_info_set_phy_address(FM1_DTSEC6,
 389                                         QSGMII_CARD_PORT4_PHY_ADDR_S2);
 390                 break;
 391         case 0x2455:
 392                 /* 2.5G SGMII on lane A, MAC 9 */
 393                 fm_info_set_phy_address(FM1_DTSEC9, 9);
 394                 /* QSGMII on lane B, MAC 1/2/5/6 */
 395                 fm_info_set_phy_address(FM1_DTSEC1,
 396                                         QSGMII_CARD_PORT1_PHY_ADDR_S2);
 397                 fm_info_set_phy_address(FM1_DTSEC2,
 398                                         QSGMII_CARD_PORT2_PHY_ADDR_S2);
 399                 fm_info_set_phy_address(FM1_DTSEC5,
 400                                         QSGMII_CARD_PORT3_PHY_ADDR_S2);
 401                 fm_info_set_phy_address(FM1_DTSEC6,
 402                                         QSGMII_CARD_PORT4_PHY_ADDR_S2);
 403                 break;
 404         case 0x2255:
 405                 /* 2.5G SGMII on lane A, MAC 9 */
 406                 fm_info_set_phy_address(FM1_DTSEC9, 9);
 407                 /* 2.5G SGMII on lane B, MAC 2 */
 408                 fm_info_set_phy_address(FM1_DTSEC2, 2);
 409                 break;
 410         case 0x3333:
 411                 /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
 412                 fm_info_set_phy_address(FM1_DTSEC9,
 413                                         SGMII_CARD_PORT1_PHY_ADDR);
 414                 fm_info_set_phy_address(FM1_DTSEC2,
 415                                         SGMII_CARD_PORT1_PHY_ADDR);
 416                 fm_info_set_phy_address(FM1_DTSEC5,
 417                                         SGMII_CARD_PORT1_PHY_ADDR);
 418                 fm_info_set_phy_address(FM1_DTSEC6,
 419                                         SGMII_CARD_PORT1_PHY_ADDR);
 420                 break;
 421         default:
 422                 printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
 423                        srds_s1);
 424                 break;
 425         }
 426
 427         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 428                 idx = i - FM1_DTSEC1;
 429                 interface = fm_info_get_enet_if(i);
 430                 switch (interface) {
 431                 case PHY_INTERFACE_MODE_SGMII:
 432                 case PHY_INTERFACE_MODE_SGMII_2500:
 433                 case PHY_INTERFACE_MODE_QSGMII:
 434                         if (interface == PHY_INTERFACE_MODE_SGMII) {
 435                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 436                                                 SGMII_FM1_DTSEC1 + idx);
 437                         } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
 438                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 439                                                 SGMII_2500_FM1_DTSEC1 + idx);
 440                         } else {
 441                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 442                                                 QSGMII_FM1_A);
 443                         }
 444
 445                         if (lane < 0)
 446                                 break;
 447
 448                         slot = lane_to_slot[lane];
 449                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 450                               idx + 1, slot);
 451                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 452                                 fm_disable_port(i);
 453
 454                         switch (slot) {
 455                         case 1:
 456                                 mdio_mux[i] = EMI1_SLOT1;
 457                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 458                                                  mdio_mux[i]));
 459                                 break;
 460                         case 2:
 461                                 mdio_mux[i] = EMI1_SLOT2;
 462                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 463                                                  mdio_mux[i]));
 464                                 break;
 465                         case 3:
 466                                 mdio_mux[i] = EMI1_SLOT3;
 467                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 468                                                  mdio_mux[i]));
 469                                 break;
 470                         case 4:
 471                                 mdio_mux[i] = EMI1_SLOT4;
 472                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 473                                                  mdio_mux[i]));
 474                                 break;
 475                         default:
 476                                 break;
 477                         }
 478                         break;
 479                 case PHY_INTERFACE_MODE_RGMII:
 480                 case PHY_INTERFACE_MODE_RGMII_TXID:
 481                         if (i == FM1_DTSEC3)
 482                                 mdio_mux[i] = EMI1_RGMII1;
 483                         else if (i == FM1_DTSEC4)
 484                                 mdio_mux[i] = EMI1_RGMII2;
 485                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 486                         break;
 487                 default:
 488                         break;
 489                 }
 490         }
 491
 492         cpu_eth_init(bis);
 493 #endif /* CONFIG_FMAN_ENET */
 494
 495         return pci_eth_init(bis);
 496 }