board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <fsl_ddr.h>
  10 #include <net.h>
  11 #include <asm/io.h>
  12 #include <hwconfig.h>
  13 #include <fdt_support.h>
  14 #include <linux/libfdt.h>
  15 #include <env_internal.h>
  16 #include <asm/arch-fsl-layerscape/soc.h>
  17 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  18 #include <i2c.h>
  19 #include <asm/arch/soc.h>
  20 #ifdef CONFIG_FSL_LS_PPA
  21 #include <asm/arch/ppa.h>
  22 #endif
  23 #include <fsl_immap.h>
  24 #include <netdev.h>
  25
  26 #include <fdtdec.h>
  27 #include <miiphy.h>
  28 #include "../common/qixis.h"
  29 #include "../drivers/net/fsl_enetc.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 int config_board_mux(void)
  34 {
  35 #ifndef CONFIG_LPUART
  36 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  37         u8 reg;
  38
  39         reg = QIXIS_READ(brdcfg[13]);
  40         /* Field| Function
  41          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  42          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  43          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  44          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  45          */
  46         reg &= ~(0xf0);
  47         reg |= 0xb0;
  48         QIXIS_WRITE(brdcfg[13], reg);
  49
  50         reg = QIXIS_READ(brdcfg[15]);
  51         /* Field| Function
  52          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  53          * CAN1 | 0= CAN #1 transceiver enabled
  54          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  55          * CAN2 | 0= CAN #2 transceiver enabled
  56          */
  57         reg &= ~(0xc0);
  58         QIXIS_WRITE(brdcfg[15], reg);
  59 #endif
  60 #endif
  61
  62         return 0;
  63 }
  64
  65 #ifdef CONFIG_LPUART
  66 u32 get_lpuart_clk(void)
  67 {
  68         return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
  69 }
  70 #endif
  71
  72 int board_init(void)
  73 {
  74 #ifdef CONFIG_ENV_IS_NOWHERE
  75         gd->env_addr = (ulong)&default_environment[0];
  76 #endif
  77
  78 #ifdef CONFIG_FSL_CAAM
  79         sec_init();
  80 #endif
  81
  82 #ifdef CONFIG_FSL_LS_PPA
  83         ppa_init();
  84 #endif
  85
  86 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  87         pci_init();
  88 #endif
  89
  90 #if defined(CONFIG_TARGET_LS1028ARDB)
  91         u8 val = I2C_MUX_CH_DEFAULT;
  92
  93 #ifndef CONFIG_DM_I2C
  94         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  95 #else
  96         struct udevice *dev;
  97
  98         if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  99                 dm_i2c_write(dev, 0x0b, &val, 1);
 100 #endif
 101 #endif
 102
 103 #if defined(CONFIG_TARGET_LS1028ARDB)
 104         u8 reg;
 105
 106         reg = QIXIS_READ(brdcfg[4]);
 107         /*
 108          * Field | Function
 109          * 3     | DisplayPort Power Enable (net DP_PWR_EN):
 110          * DPPWR | 0= DP_PWR is enabled.
 111          */
 112         reg &= ~(DP_PWD_EN_DEFAULT_MASK);
 113         QIXIS_WRITE(brdcfg[4], reg);
 114 #endif
 115         return 0;
 116 }
 117
 118 int board_eth_init(bd_t *bis)
 119 {
 120         return pci_eth_init(bis);
 121 }
 122
 123 #ifdef CONFIG_MISC_INIT_R
 124 int misc_init_r(void)
 125 {
 126         config_board_mux();
 127
 128         return 0;
 129 }
 130 #endif
 131
 132 int board_early_init_f(void)
 133 {
 134 #ifdef CONFIG_LPUART
 135         u8 uart;
 136 #endif
 137
 138 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 139         i2c_early_init_f();
 140 #endif
 141
 142         fsl_lsch3_early_init_f();
 143
 144 #ifdef CONFIG_LPUART
 145         /*
 146          * Field| Function
 147          * --------------------------------------------------------------
 148          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
 149          * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
 150          * --------------------------------------------------------------
 151          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
 152          * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
 153          */
 154         /* use lpuart0 as system console */
 155         uart = QIXIS_READ(brdcfg[13]);
 156         uart &= ~CFG_LPUART_MUX_MASK;
 157         uart |= CFG_LPUART_EN;
 158         QIXIS_WRITE(brdcfg[13], uart);
 159 #endif
 160
 161         return 0;
 162 }
 163
 164 void detail_board_ddr_info(void)
 165 {
 166         puts("\nDDR    ");
 167         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 168         print_ddr_info(0);
 169 }
 170
 171 int esdhc_status_fixup(void *blob, const char *compat)
 172 {
 173         void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
 174         char esdhc1_path[] = "/soc/mmc@2140000";
 175         char esdhc2_path[] = "/soc/mmc@2150000";
 176         char dspi1_path[] = "/soc/spi@2100000";
 177         char dspi2_path[] = "/soc/spi@2110000";
 178         u32 mux_sdhc1, mux_sdhc2;
 179         u32 io = 0;
 180
 181         /*
 182          * The PMUX IO-expander for mux select is used to control
 183          * the muxing of various onboard interfaces.
 184          */
 185
 186         io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
 187         mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
 188
 189         /* Disable esdhc1/dspi1 if not selected. */
 190         if (mux_sdhc1 != 0)
 191                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 192                                  sizeof("disabled"), 1);
 193         if (mux_sdhc1 != 2)
 194                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 195                                  sizeof("disabled"), 1);
 196
 197         io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
 198         mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
 199
 200         /* Disable esdhc2/dspi2 if not selected. */
 201         if (mux_sdhc2 != 0)
 202                 do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
 203                                  sizeof("disabled"), 1);
 204         if (mux_sdhc2 != 2)
 205                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 206                                  sizeof("disabled"), 1);
 207
 208         return 0;
 209 }
 210
 211 #ifdef CONFIG_OF_BOARD_SETUP
 212 int ft_board_setup(void *blob, bd_t *bd)
 213 {
 214         u64 base[CONFIG_NR_DRAM_BANKS];
 215         u64 size[CONFIG_NR_DRAM_BANKS];
 216
 217         ft_cpu_setup(blob, bd);
 218
 219         /* fixup DT for the two GPP DDR banks */
 220         base[0] = gd->bd->bi_dram[0].start;
 221         size[0] = gd->bd->bi_dram[0].size;
 222         base[1] = gd->bd->bi_dram[1].start;
 223         size[1] = gd->bd->bi_dram[1].size;
 224
 225 #ifdef CONFIG_RESV_RAM
 226         /* reduce size if reserved memory is within this bank */
 227         if (gd->arch.resv_ram >= base[0] &&
 228             gd->arch.resv_ram < base[0] + size[0])
 229                 size[0] = gd->arch.resv_ram - base[0];
 230         else if (gd->arch.resv_ram >= base[1] &&
 231                  gd->arch.resv_ram < base[1] + size[1])
 232                 size[1] = gd->arch.resv_ram - base[1];
 233 #endif
 234
 235         fdt_fixup_memory_banks(blob, base, size, 2);
 236
 237         fdt_fixup_icid(blob);
 238
 239 #ifdef CONFIG_FSL_ENETC
 240         fdt_fixup_enetc_mac(blob);
 241 #endif
 242
 243         return 0;
 244 }
 245 #endif
 246
 247 #ifdef CONFIG_FSL_QIXIS
 248 int checkboard(void)
 249 {
 250 #ifdef CONFIG_TFABOOT
 251         enum boot_src src = get_boot_src();
 252 #endif
 253         u8 sw;
 254
 255         int clock;
 256         char *board;
 257         char buf[64] = {0};
 258         static const char *freq[6] = {"100.00", "125.00", "156.25",
 259                                         "161.13", "322.26", "100.00 SS"};
 260
 261         cpu_name(buf);
 262         /* find the board details */
 263         sw = QIXIS_READ(id);
 264
 265         switch (sw) {
 266         case 0x46:
 267                 board = "QDS";
 268                 break;
 269         case 0x47:
 270                 board = "RDB";
 271                 break;
 272         case 0x49:
 273                 board = "HSSI";
 274                 break;
 275         default:
 276                 board = "unknown";
 277                 break;
 278         }
 279
 280         sw = QIXIS_READ(arch);
 281         printf("Board: %s-%s, Version: %c, boot from ",
 282                buf, board, (sw & 0xf) + 'A' - 1);
 283
 284         sw = QIXIS_READ(brdcfg[0]);
 285         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 286
 287 #ifdef CONFIG_TFABOOT
 288         if (src == BOOT_SOURCE_SD_MMC) {
 289                 puts("SD\n");
 290         } else if (src == BOOT_SOURCE_SD_MMC2) {
 291                 puts("eMMC\n");
 292         } else {
 293 #endif
 294 #ifdef CONFIG_SD_BOOT
 295                 puts("SD\n");
 296 #elif defined(CONFIG_EMMC_BOOT)
 297                 puts("eMMC\n");
 298 #else
 299                 switch (sw) {
 300                 case 0:
 301                 case 4:
 302                         printf("NOR\n");
 303                         break;
 304                 case 1:
 305                         printf("NAND\n");
 306                         break;
 307                 default:
 308                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 309                         break;
 310                 }
 311 #endif
 312 #ifdef CONFIG_TFABOOT
 313         }
 314 #endif
 315
 316         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 317         puts("SERDES1 Reference : ");
 318
 319         sw = QIXIS_READ(brdcfg[2]);
 320 #ifdef CONFIG_TARGET_LS1028ARDB
 321         clock = (sw >> 6) & 3;
 322 #else
 323         clock = (sw >> 4) & 0xf;
 324 #endif
 325
 326         printf("Clock1 = %sMHz ", freq[clock]);
 327 #ifdef CONFIG_TARGET_LS1028ARDB
 328         clock = (sw >> 4) & 3;
 329 #else
 330         clock = sw & 0xf;
 331 #endif
 332         printf("Clock2 = %sMHz\n", freq[clock]);
 333
 334         return 0;
 335 }
 336 #endif