board/freescale/ls1021atwr/ls1021atwr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/immap_ls102xa.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include <asm/arch/ls102xa_devdis.h>
  13 #include <asm/arch/ls102xa_soc.h>
  14 #include <hwconfig.h>
  15 #include <mmc.h>
  16 #include <fsl_csu.h>
  17 #include <fsl_esdhc.h>
  18 #include <fsl_ifc.h>
  19 #include <fsl_immap.h>
  20 #include <netdev.h>
  21 #include <fsl_mdio.h>
  22 #include <tsec.h>
  23 #include <fsl_sec.h>
  24 #include <fsl_devdis.h>
  25 #include <spl.h>
  26 #include "../common/sleep.h"
  27 #ifdef CONFIG_U_QE
  28 #include <fsl_qe.h>
  29 #endif
  30 #include <fsl_validate.h>
  31
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define VERSION_MASK            0x00FF
  36 #define BANK_MASK               0x0001
  37 #define CONFIG_RESET            0x1
  38 #define INIT_RESET              0x1
  39
  40 #define CPLD_SET_MUX_SERDES     0x20
  41 #define CPLD_SET_BOOT_BANK      0x40
  42
  43 #define BOOT_FROM_UPPER_BANK    0x0
  44 #define BOOT_FROM_LOWER_BANK    0x1
  45
  46 #define LANEB_SATA              (0x01)
  47 #define LANEB_SGMII1            (0x02)
  48 #define LANEC_SGMII1            (0x04)
  49 #define LANEC_PCIEX1            (0x08)
  50 #define LANED_PCIEX2            (0x10)
  51 #define LANED_SGMII2            (0x20)
  52
  53 #define MASK_LANE_B             0x1
  54 #define MASK_LANE_C             0x2
  55 #define MASK_LANE_D             0x4
  56 #define MASK_SGMII              0x8
  57
  58 #define KEEP_STATUS             0x0
  59 #define NEED_RESET              0x1
  60
  61 #define SOFT_MUX_ON_I2C3_IFC    0x2
  62 #define SOFT_MUX_ON_CAN3_USB2   0x8
  63 #define SOFT_MUX_ON_QE_LCD      0x10
  64
  65 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  66 #define PIN_I2C3_IFC_MUX_IFC    0x1
  67 #define PIN_CAN3_USB2_MUX_USB2  0x0
  68 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  69 #define PIN_QE_LCD_MUX_LCD      0x0
  70 #define PIN_QE_LCD_MUX_QE       0x1
  71
  72 struct cpld_data {
  73         u8 cpld_ver;            /* cpld revision */
  74         u8 cpld_ver_sub;        /* cpld sub revision */
  75         u8 pcba_ver;            /* pcb revision number */
  76         u8 system_rst;          /* reset system by cpld */
  77         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  78         u8 cfg_rcw_src1;        /* Reset config word 1 */
  79         u8 cfg_rcw_src2;        /* Reset config word 2 */
  80         u8 vbank;               /* Flash bank selection Control */
  81         u8 gpio;                /* GPIO for TWR-ELEV */
  82         u8 i2c3_ifc_mux;
  83         u8 mux_spi2;
  84         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  85         u8 qe_lcd_mux;          /* QE and LCD Selection */
  86         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  87         u8 global_rst;          /* reset with init CPLD reg to default */
  88         u8 rev1;                /* Reserved */
  89         u8 rev2;                /* Reserved */
  90 };
  91
  92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  93 static void cpld_show(void)
  94 {
  95         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  96
  97         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
  98                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
  99                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 100                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 101                in_8(&cpld_data->vbank) & BANK_MASK);
 102
 103 #ifdef CONFIG_DEBUG
 104         printf("soft_mux_on =%x\n",
 105                in_8(&cpld_data->soft_mux_on));
 106         printf("cfg_rcw_src1 =%x\n",
 107                in_8(&cpld_data->cfg_rcw_src1));
 108         printf("cfg_rcw_src2 =%x\n",
 109                in_8(&cpld_data->cfg_rcw_src2));
 110         printf("vbank =%x\n",
 111                in_8(&cpld_data->vbank));
 112         printf("gpio =%x\n",
 113                in_8(&cpld_data->gpio));
 114         printf("i2c3_ifc_mux =%x\n",
 115                in_8(&cpld_data->i2c3_ifc_mux));
 116         printf("mux_spi2 =%x\n",
 117                in_8(&cpld_data->mux_spi2));
 118         printf("can3_usb2_mux =%x\n",
 119                in_8(&cpld_data->can3_usb2_mux));
 120         printf("qe_lcd_mux =%x\n",
 121                in_8(&cpld_data->qe_lcd_mux));
 122         printf("serdes_mux =%x\n",
 123                in_8(&cpld_data->serdes_mux));
 124 #endif
 125 }
 126 #endif
 127
 128 int checkboard(void)
 129 {
 130         puts("Board: LS1021ATWR\n");
 131 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 132         cpld_show();
 133 #endif
 134
 135         return 0;
 136 }
 137
 138 void ddrmc_init(void)
 139 {
 140         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 141         u32 temp_sdram_cfg, tmp;
 142
 143         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 144
 145         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 146         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 147
 148         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 149         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 150         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 151         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 152         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 153         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 154
 155 #ifdef CONFIG_DEEP_SLEEP
 156         if (is_warm_boot()) {
 157                 out_be32(&ddr->sdram_cfg_2,
 158                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 159                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 160                 out_be32(&ddr->init_ext_addr, (1 << 31));
 161
 162                 /* DRAM VRef will not be trained */
 163                 out_be32(&ddr->ddr_cdr2,
 164                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 165         } else
 166 #endif
 167         {
 168                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 169                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 170         }
 171
 172         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 173         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 174
 175         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 176
 177         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 178
 179         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 180         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 181
 182         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 183
 184         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 185         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 186
 187         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 188
 189         /* DDR erratum A-009942 */
 190         tmp = in_be32(&ddr->debug[28]);
 191         out_be32(&ddr->debug[28], tmp | 0x0070006f);
 192
 193         udelay(1);
 194
 195 #ifdef CONFIG_DEEP_SLEEP
 196         if (is_warm_boot()) {
 197                 /* enter self-refresh */
 198                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 199                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 200                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 201
 202                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 203         } else
 204 #endif
 205                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 206
 207         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 208
 209 #ifdef CONFIG_DEEP_SLEEP
 210         if (is_warm_boot()) {
 211                 /* exit self-refresh */
 212                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 213                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 214                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 215         }
 216 #endif
 217 }
 218
 219 int dram_init(void)
 220 {
 221 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 222         ddrmc_init();
 223 #endif
 224
 225         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 226
 227 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 228         fsl_dp_resume();
 229 #endif
 230
 231         return 0;
 232 }
 233
 234 #ifdef CONFIG_FSL_ESDHC
 235 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 236         {CONFIG_SYS_FSL_ESDHC_ADDR},
 237 };
 238
 239 int board_mmc_init(bd_t *bis)
 240 {
 241         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 242
 243         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 244 }
 245 #endif
 246
 247 int board_eth_init(bd_t *bis)
 248 {
 249 #ifdef CONFIG_TSEC_ENET
 250         struct fsl_pq_mdio_info mdio_info;
 251         struct tsec_info_struct tsec_info[4];
 252         int num = 0;
 253
 254 #ifdef CONFIG_TSEC1
 255         SET_STD_TSEC_INFO(tsec_info[num], 1);
 256         if (is_serdes_configured(SGMII_TSEC1)) {
 257                 puts("eTSEC1 is in sgmii mode.\n");
 258                 tsec_info[num].flags |= TSEC_SGMII;
 259         }
 260         num++;
 261 #endif
 262 #ifdef CONFIG_TSEC2
 263         SET_STD_TSEC_INFO(tsec_info[num], 2);
 264         if (is_serdes_configured(SGMII_TSEC2)) {
 265                 puts("eTSEC2 is in sgmii mode.\n");
 266                 tsec_info[num].flags |= TSEC_SGMII;
 267         }
 268         num++;
 269 #endif
 270 #ifdef CONFIG_TSEC3
 271         SET_STD_TSEC_INFO(tsec_info[num], 3);
 272         tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
 273         num++;
 274 #endif
 275         if (!num) {
 276                 printf("No TSECs initialized\n");
 277                 return 0;
 278         }
 279
 280         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 281         mdio_info.name = DEFAULT_MII_NAME;
 282         fsl_pq_mdio_init(bis, &mdio_info);
 283
 284         tsec_eth_init(bis, tsec_info, num);
 285 #endif
 286
 287         return pci_eth_init(bis);
 288 }
 289
 290 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 291 static void convert_serdes_mux(int type, int need_reset)
 292 {
 293         char current_serdes;
 294         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 295
 296         current_serdes = cpld_data->serdes_mux;
 297
 298         switch (type) {
 299         case LANEB_SATA:
 300                 current_serdes &= ~MASK_LANE_B;
 301                 break;
 302         case LANEB_SGMII1:
 303                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 304                 break;
 305         case LANEC_SGMII1:
 306                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 307                 break;
 308         case LANED_SGMII2:
 309                 current_serdes |= MASK_LANE_D;
 310                 break;
 311         case LANEC_PCIEX1:
 312                 current_serdes |= MASK_LANE_C;
 313                 break;
 314         case (LANED_PCIEX2 | LANEC_PCIEX1):
 315                 current_serdes |= MASK_LANE_C;
 316                 current_serdes &= ~MASK_LANE_D;
 317                 break;
 318         default:
 319                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 320                 return;
 321         }
 322
 323         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 324         cpld_data->serdes_mux = current_serdes;
 325
 326         if (need_reset == 1) {
 327                 printf("Reset board to enable configuration\n");
 328                 cpld_data->system_rst = CONFIG_RESET;
 329         }
 330 }
 331
 332 int config_serdes_mux(void)
 333 {
 334         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 335         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 336
 337         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 338         switch (protocol) {
 339         case 0x10:
 340                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 341                 convert_serdes_mux(LANED_PCIEX2 |
 342                                 LANEC_PCIEX1, KEEP_STATUS);
 343                 break;
 344         case 0x20:
 345                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 346                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 347                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 348                 break;
 349         case 0x30:
 350                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 351                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 352                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 353                 break;
 354         case 0x70:
 355                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 356                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 357                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 358                 break;
 359         }
 360
 361         return 0;
 362 }
 363 #endif
 364
 365 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 366 int config_board_mux(void)
 367 {
 368         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 369         int conflict_flag;
 370
 371         conflict_flag = 0;
 372         if (hwconfig("i2c3")) {
 373                 conflict_flag++;
 374                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 375                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 376         }
 377
 378         if (hwconfig("ifc")) {
 379                 conflict_flag++;
 380                 /* some signals can not enable simultaneous*/
 381                 if (conflict_flag > 1)
 382                         goto conflict;
 383                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 384                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 385         }
 386
 387         conflict_flag = 0;
 388         if (hwconfig("usb2")) {
 389                 conflict_flag++;
 390                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 391                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 392         }
 393
 394         if (hwconfig("can3")) {
 395                 conflict_flag++;
 396                 /* some signals can not enable simultaneous*/
 397                 if (conflict_flag > 1)
 398                         goto conflict;
 399                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 400                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 401         }
 402
 403         conflict_flag = 0;
 404         if (hwconfig("lcd")) {
 405                 conflict_flag++;
 406                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 407                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 408         }
 409
 410         if (hwconfig("qe")) {
 411                 conflict_flag++;
 412                 /* some signals can not enable simultaneous*/
 413                 if (conflict_flag > 1)
 414                         goto conflict;
 415                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 416                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 417         }
 418
 419         return 0;
 420
 421 conflict:
 422         printf("WARNING: pin conflict! MUX setting may failed!\n");
 423         return 0;
 424 }
 425 #endif
 426
 427 int board_early_init_f(void)
 428 {
 429         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 430
 431 #ifdef CONFIG_TSEC_ENET
 432         /* clear BD & FR bits for BE BD's and frame data */
 433         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 434         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 435 #endif
 436
 437 #ifdef CONFIG_FSL_IFC
 438         init_early_memctl_regs();
 439 #endif
 440
 441         arch_soc_init();
 442
 443 #if defined(CONFIG_DEEP_SLEEP)
 444         if (is_warm_boot()) {
 445                 timer_init();
 446                 dram_init();
 447         }
 448 #endif
 449
 450         return 0;
 451 }
 452
 453 #ifdef CONFIG_SPL_BUILD
 454 void board_init_f(ulong dummy)
 455 {
 456         void (*second_uboot)(void);
 457
 458         /* Clear the BSS */
 459         memset(__bss_start, 0, __bss_end - __bss_start);
 460
 461         get_clocks();
 462
 463 #if defined(CONFIG_DEEP_SLEEP)
 464         if (is_warm_boot())
 465                 fsl_dp_disable_console();
 466 #endif
 467
 468         preloader_console_init();
 469
 470         dram_init();
 471
 472         /* Allow OCRAM access permission as R/W */
 473 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 474         enable_layerscape_ns_access();
 475 #endif
 476
 477         /*
 478          * if it is woken up from deep sleep, then jump to second
 479          * stage uboot and continue executing without recopying
 480          * it from SD since it has already been reserved in memeory
 481          * in last boot.
 482          */
 483         if (is_warm_boot()) {
 484                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 485                 second_uboot();
 486         }
 487
 488         board_init_r(NULL, 0);
 489 }
 490 #endif
 491
 492 #ifdef CONFIG_DEEP_SLEEP
 493 /* program the regulator (MC34VR500) to support deep sleep */
 494 void ls1twr_program_regulator(void)
 495 {
 496         unsigned int i2c_bus;
 497         u8 i2c_device_id;
 498
 499 #define LS1TWR_I2C_BUS_MC34VR500        1
 500 #define MC34VR500_ADDR                  0x8
 501 #define MC34VR500_DEVICEID              0x4
 502 #define MC34VR500_DEVICEID_MASK         0x0f
 503
 504         i2c_bus = i2c_get_bus_num();
 505         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 506         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
 507                                         MC34VR500_DEVICEID_MASK;
 508         if (i2c_device_id != MC34VR500_DEVICEID) {
 509                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 510                 return;
 511         }
 512
 513         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
 514         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
 515         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
 516         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
 517         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 518
 519         i2c_set_bus_num(i2c_bus);
 520 }
 521 #endif
 522
 523 int board_init(void)
 524 {
 525 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 526         erratum_a010315();
 527 #endif
 528
 529 #ifndef CONFIG_SYS_FSL_NO_SERDES
 530         fsl_serdes_init();
 531 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 532         config_serdes_mux();
 533 #endif
 534 #endif
 535
 536         ls102xa_smmu_stream_id_init();
 537
 538 #ifdef CONFIG_U_QE
 539         u_qe_init();
 540 #endif
 541
 542 #ifdef CONFIG_DEEP_SLEEP
 543         ls1twr_program_regulator();
 544 #endif
 545         return 0;
 546 }
 547
 548 #if defined(CONFIG_SPL_BUILD)
 549 void spl_board_init(void)
 550 {
 551         ls102xa_smmu_stream_id_init();
 552 }
 553 #endif
 554
 555 #ifdef CONFIG_BOARD_LATE_INIT
 556 int board_late_init(void)
 557 {
 558 #ifdef CONFIG_CHAIN_OF_TRUST
 559         fsl_setenv_chain_of_trust();
 560 #endif
 561
 562         return 0;
 563 }
 564 #endif
 565
 566 #if defined(CONFIG_MISC_INIT_R)
 567 int misc_init_r(void)
 568 {
 569 #ifdef CONFIG_FSL_DEVICE_DISABLE
 570         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 571 #endif
 572 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 573         config_board_mux();
 574 #endif
 575
 576 #ifdef CONFIG_FSL_CAAM
 577         return sec_init();
 578 #endif
 579 }
 580 #endif
 581
 582 #if defined(CONFIG_DEEP_SLEEP)
 583 void board_sleep_prepare(void)
 584 {
 585 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 586         enable_layerscape_ns_access();
 587 #endif
 588 }
 589 #endif
 590
 591 int ft_board_setup(void *blob, bd_t *bd)
 592 {
 593         ft_cpu_setup(blob, bd);
 594
 595 #ifdef CONFIG_PCI
 596         ft_pci_setup(blob, bd);
 597 #endif
 598
 599         return 0;
 600 }
 601
 602 u8 flash_read8(void *addr)
 603 {
 604         return __raw_readb(addr + 1);
 605 }
 606
 607 void flash_write16(u16 val, void *addr)
 608 {
 609         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 610
 611         __raw_writew(shftval, addr);
 612 }
 613
 614 u16 flash_read16(void *addr)
 615 {
 616         u16 val = __raw_readw(addr);
 617
 618         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 619 }
 620
 621 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
 622         && !defined(CONFIG_SPL_BUILD)
 623 static void convert_flash_bank(char bank)
 624 {
 625         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 626
 627         printf("Now switch to boot from flash bank %d.\n", bank);
 628         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 629         cpld_data->vbank = bank;
 630
 631         printf("Reset board to enable configuration.\n");
 632         cpld_data->system_rst = CONFIG_RESET;
 633 }
 634
 635 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 636                           char * const argv[])
 637 {
 638         if (argc != 2)
 639                 return CMD_RET_USAGE;
 640         if (strcmp(argv[1], "0") == 0)
 641                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 642         else if (strcmp(argv[1], "1") == 0)
 643                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 644         else
 645                 return CMD_RET_USAGE;
 646
 647         return 0;
 648 }
 649
 650 U_BOOT_CMD(
 651         boot_bank, 2, 0, flash_bank_cmd,
 652         "Flash bank Selection Control",
 653         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 654 );
 655
 656 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 657                           char * const argv[])
 658 {
 659         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 660
 661         if (argc > 2)
 662                 return CMD_RET_USAGE;
 663         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 664                 cpld_data->system_rst = CONFIG_RESET;
 665         else if (strcmp(argv[1], "init") == 0)
 666                 cpld_data->global_rst = INIT_RESET;
 667         else
 668                 return CMD_RET_USAGE;
 669
 670         return 0;
 671 }
 672
 673 U_BOOT_CMD(
 674         cpld_reset, 2, 0, cpld_reset_cmd,
 675         "Reset via CPLD",
 676         "conf\n"
 677         "       -reset with current CPLD configuration\n"
 678         "init\n"
 679         "       -reset and initial CPLD configuration with default value"
 680
 681 );
 682
 683 static void print_serdes_mux(void)
 684 {
 685         char current_serdes;
 686         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 687
 688         current_serdes = cpld_data->serdes_mux;
 689
 690         printf("Serdes Lane B: ");
 691         if ((current_serdes & MASK_LANE_B) == 0)
 692                 printf("SATA,\n");
 693         else
 694                 printf("SGMII 1,\n");
 695
 696         printf("Serdes Lane C: ");
 697         if ((current_serdes & MASK_LANE_C) == 0)
 698                 printf("SGMII 1,\n");
 699         else
 700                 printf("PCIe,\n");
 701
 702         printf("Serdes Lane D: ");
 703         if ((current_serdes & MASK_LANE_D) == 0)
 704                 printf("PCIe,\n");
 705         else
 706                 printf("SGMII 2,\n");
 707
 708         printf("SGMII 1 is on lane ");
 709         if ((current_serdes & MASK_SGMII) == 0)
 710                 printf("C.\n");
 711         else
 712                 printf("B.\n");
 713 }
 714
 715 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 716                           char * const argv[])
 717 {
 718         if (argc != 2)
 719                 return CMD_RET_USAGE;
 720         if (strcmp(argv[1], "sata") == 0) {
 721                 printf("Set serdes lane B to SATA.\n");
 722                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 723         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 724                 printf("Set serdes lane B to SGMII 1.\n");
 725                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 726         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 727                 printf("Set serdes lane C to SGMII 1.\n");
 728                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 729         } else if (strcmp(argv[1], "sgmii2") == 0) {
 730                 printf("Set serdes lane D to SGMII 2.\n");
 731                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 732         } else if (strcmp(argv[1], "pciex1") == 0) {
 733                 printf("Set serdes lane C to PCIe X1.\n");
 734                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 735         } else if (strcmp(argv[1], "pciex2") == 0) {
 736                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 737                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 738         } else if (strcmp(argv[1], "show") == 0) {
 739                 print_serdes_mux();
 740         } else {
 741                 return CMD_RET_USAGE;
 742         }
 743
 744         return 0;
 745 }
 746
 747 U_BOOT_CMD(
 748         lane_bank, 2, 0, serdes_mux_cmd,
 749         "Multiplexed function setting for SerDes Lanes",
 750         "sata\n"
 751         "       -change lane B to sata\n"
 752         "lane_bank sgmii1b\n"
 753         "       -change lane B to SGMII1\n"
 754         "lane_bank sgmii1c\n"
 755         "       -change lane C to SGMII1\n"
 756         "lane_bank sgmii2\n"
 757         "       -change lane D to SGMII2\n"
 758         "lane_bank pciex1\n"
 759         "       -change lane C to PCIeX1\n"
 760         "lane_bank pciex2\n"
 761         "       -change lane C & lane D to PCIeX2\n"
 762         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 763 );
 764 #endif