board/freescale/ls1021atwr/ls1021atwr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <clock_legacy.h>
   9 #include <command.h>
  10 #include <fdt_support.h>
  11 #include <i2c.h>
  12 #include <init.h>
  13 #include <net.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/immap_ls102xa.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/fsl_serdes.h>
  18 #include <asm/arch/ls102xa_devdis.h>
  19 #include <asm/arch/ls102xa_soc.h>
  20 #include <hwconfig.h>
  21 #include <mmc.h>
  22 #include <fsl_csu.h>
  23 #include <fsl_ifc.h>
  24 #include <fsl_immap.h>
  25 #include <netdev.h>
  26 #include <fsl_mdio.h>
  27 #include <tsec.h>
  28 #include <fsl_sec.h>
  29 #include <fsl_devdis.h>
  30 #include <spl.h>
  31 #include "../common/sleep.h"
  32 #ifdef CONFIG_U_QE
  33 #include <fsl_qe.h>
  34 #endif
  35 #include <fsl_validate.h>
  36
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define VERSION_MASK            0x00FF
  41 #define BANK_MASK               0x0001
  42 #define CONFIG_RESET            0x1
  43 #define INIT_RESET              0x1
  44
  45 #define CPLD_SET_MUX_SERDES     0x20
  46 #define CPLD_SET_BOOT_BANK      0x40
  47
  48 #define BOOT_FROM_UPPER_BANK    0x0
  49 #define BOOT_FROM_LOWER_BANK    0x1
  50
  51 #define LANEB_SATA              (0x01)
  52 #define LANEB_SGMII1            (0x02)
  53 #define LANEC_SGMII1            (0x04)
  54 #define LANEC_PCIEX1            (0x08)
  55 #define LANED_PCIEX2            (0x10)
  56 #define LANED_SGMII2            (0x20)
  57
  58 #define MASK_LANE_B             0x1
  59 #define MASK_LANE_C             0x2
  60 #define MASK_LANE_D             0x4
  61 #define MASK_SGMII              0x8
  62
  63 #define KEEP_STATUS             0x0
  64 #define NEED_RESET              0x1
  65
  66 #define SOFT_MUX_ON_I2C3_IFC    0x2
  67 #define SOFT_MUX_ON_CAN3_USB2   0x8
  68 #define SOFT_MUX_ON_QE_LCD      0x10
  69
  70 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  71 #define PIN_I2C3_IFC_MUX_IFC    0x1
  72 #define PIN_CAN3_USB2_MUX_USB2  0x0
  73 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  74 #define PIN_QE_LCD_MUX_LCD      0x0
  75 #define PIN_QE_LCD_MUX_QE       0x1
  76
  77 struct cpld_data {
  78         u8 cpld_ver;            /* cpld revision */
  79         u8 cpld_ver_sub;        /* cpld sub revision */
  80         u8 pcba_ver;            /* pcb revision number */
  81         u8 system_rst;          /* reset system by cpld */
  82         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  83         u8 cfg_rcw_src1;        /* Reset config word 1 */
  84         u8 cfg_rcw_src2;        /* Reset config word 2 */
  85         u8 vbank;               /* Flash bank selection Control */
  86         u8 gpio;                /* GPIO for TWR-ELEV */
  87         u8 i2c3_ifc_mux;
  88         u8 mux_spi2;
  89         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  90         u8 qe_lcd_mux;          /* QE and LCD Selection */
  91         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  92         u8 global_rst;          /* reset with init CPLD reg to default */
  93         u8 rev1;                /* Reserved */
  94         u8 rev2;                /* Reserved */
  95 };
  96
  97 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  98 static void cpld_show(void)
  99 {
 100         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 101
 102         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
 103                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
 104                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 105                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 106                in_8(&cpld_data->vbank) & BANK_MASK);
 107
 108 #ifdef CONFIG_DEBUG
 109         printf("soft_mux_on =%x\n",
 110                in_8(&cpld_data->soft_mux_on));
 111         printf("cfg_rcw_src1 =%x\n",
 112                in_8(&cpld_data->cfg_rcw_src1));
 113         printf("cfg_rcw_src2 =%x\n",
 114                in_8(&cpld_data->cfg_rcw_src2));
 115         printf("vbank =%x\n",
 116                in_8(&cpld_data->vbank));
 117         printf("gpio =%x\n",
 118                in_8(&cpld_data->gpio));
 119         printf("i2c3_ifc_mux =%x\n",
 120                in_8(&cpld_data->i2c3_ifc_mux));
 121         printf("mux_spi2 =%x\n",
 122                in_8(&cpld_data->mux_spi2));
 123         printf("can3_usb2_mux =%x\n",
 124                in_8(&cpld_data->can3_usb2_mux));
 125         printf("qe_lcd_mux =%x\n",
 126                in_8(&cpld_data->qe_lcd_mux));
 127         printf("serdes_mux =%x\n",
 128                in_8(&cpld_data->serdes_mux));
 129 #endif
 130 }
 131 #endif
 132
 133 int checkboard(void)
 134 {
 135         puts("Board: LS1021ATWR\n");
 136 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 137         cpld_show();
 138 #endif
 139
 140         return 0;
 141 }
 142
 143 void ddrmc_init(void)
 144 {
 145         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 146         u32 temp_sdram_cfg, tmp;
 147
 148         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 149
 150         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 151         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 152
 153         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 154         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 155         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 156         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 157         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 158         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 159
 160 #ifdef CONFIG_DEEP_SLEEP
 161         if (is_warm_boot()) {
 162                 out_be32(&ddr->sdram_cfg_2,
 163                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 164                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 165                 out_be32(&ddr->init_ext_addr, (1 << 31));
 166
 167                 /* DRAM VRef will not be trained */
 168                 out_be32(&ddr->ddr_cdr2,
 169                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 170         } else
 171 #endif
 172         {
 173                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 174                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 175         }
 176
 177         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 178         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 179
 180         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 181
 182         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 183
 184         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 185         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 186
 187         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 188
 189         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 190         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 191
 192         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 193
 194         /* DDR erratum A-009942 */
 195         tmp = in_be32(&ddr->debug[28]);
 196         out_be32(&ddr->debug[28], tmp | 0x0070006f);
 197
 198         udelay(1);
 199
 200 #ifdef CONFIG_DEEP_SLEEP
 201         if (is_warm_boot()) {
 202                 /* enter self-refresh */
 203                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 204                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 205                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 206
 207                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 208         } else
 209 #endif
 210                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 211
 212         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 213
 214 #ifdef CONFIG_DEEP_SLEEP
 215         if (is_warm_boot()) {
 216                 /* exit self-refresh */
 217                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 218                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 219                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 220         }
 221 #endif
 222 }
 223
 224 int dram_init(void)
 225 {
 226 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 227         ddrmc_init();
 228 #endif
 229
 230         erratum_a008850_post();
 231
 232         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 233
 234 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 235         fsl_dp_resume();
 236 #endif
 237
 238         return 0;
 239 }
 240
 241 int board_eth_init(bd_t *bis)
 242 {
 243         return pci_eth_init(bis);
 244 }
 245
 246 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 247 static void convert_serdes_mux(int type, int need_reset)
 248 {
 249         char current_serdes;
 250         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 251
 252         current_serdes = cpld_data->serdes_mux;
 253
 254         switch (type) {
 255         case LANEB_SATA:
 256                 current_serdes &= ~MASK_LANE_B;
 257                 break;
 258         case LANEB_SGMII1:
 259                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 260                 break;
 261         case LANEC_SGMII1:
 262                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 263                 break;
 264         case LANED_SGMII2:
 265                 current_serdes |= MASK_LANE_D;
 266                 break;
 267         case LANEC_PCIEX1:
 268                 current_serdes |= MASK_LANE_C;
 269                 break;
 270         case (LANED_PCIEX2 | LANEC_PCIEX1):
 271                 current_serdes |= MASK_LANE_C;
 272                 current_serdes &= ~MASK_LANE_D;
 273                 break;
 274         default:
 275                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 276                 return;
 277         }
 278
 279         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 280         cpld_data->serdes_mux = current_serdes;
 281
 282         if (need_reset == 1) {
 283                 printf("Reset board to enable configuration\n");
 284                 cpld_data->system_rst = CONFIG_RESET;
 285         }
 286 }
 287
 288 int config_serdes_mux(void)
 289 {
 290         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 291         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 292
 293         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 294         switch (protocol) {
 295         case 0x10:
 296                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 297                 convert_serdes_mux(LANED_PCIEX2 |
 298                                 LANEC_PCIEX1, KEEP_STATUS);
 299                 break;
 300         case 0x20:
 301                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 302                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 303                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 304                 break;
 305         case 0x30:
 306                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 307                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 308                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 309                 break;
 310         case 0x70:
 311                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 312                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 313                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 314                 break;
 315         }
 316
 317         return 0;
 318 }
 319 #endif
 320
 321 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 322 int config_board_mux(void)
 323 {
 324         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 325         int conflict_flag;
 326
 327         conflict_flag = 0;
 328         if (hwconfig("i2c3")) {
 329                 conflict_flag++;
 330                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 331                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 332         }
 333
 334         if (hwconfig("ifc")) {
 335                 conflict_flag++;
 336                 /* some signals can not enable simultaneous*/
 337                 if (conflict_flag > 1)
 338                         goto conflict;
 339                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 340                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 341         }
 342
 343         conflict_flag = 0;
 344         if (hwconfig("usb2")) {
 345                 conflict_flag++;
 346                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 347                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 348         }
 349
 350         if (hwconfig("can3")) {
 351                 conflict_flag++;
 352                 /* some signals can not enable simultaneous*/
 353                 if (conflict_flag > 1)
 354                         goto conflict;
 355                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 356                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 357         }
 358
 359         conflict_flag = 0;
 360         if (hwconfig("lcd")) {
 361                 conflict_flag++;
 362                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 363                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 364         }
 365
 366         if (hwconfig("qe")) {
 367                 conflict_flag++;
 368                 /* some signals can not enable simultaneous*/
 369                 if (conflict_flag > 1)
 370                         goto conflict;
 371                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 372                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 373         }
 374
 375         return 0;
 376
 377 conflict:
 378         printf("WARNING: pin conflict! MUX setting may failed!\n");
 379         return 0;
 380 }
 381 #endif
 382
 383 int board_early_init_f(void)
 384 {
 385         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 386
 387 #ifdef CONFIG_TSEC_ENET
 388         /* clear BD & FR bits for BE BD's and frame data */
 389         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 390         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 391 #endif
 392
 393 #ifdef CONFIG_FSL_IFC
 394         init_early_memctl_regs();
 395 #endif
 396
 397         arch_soc_init();
 398
 399 #if defined(CONFIG_DEEP_SLEEP)
 400         if (is_warm_boot()) {
 401                 timer_init();
 402                 dram_init();
 403         }
 404 #endif
 405
 406         return 0;
 407 }
 408
 409 #ifdef CONFIG_SPL_BUILD
 410 void board_init_f(ulong dummy)
 411 {
 412         void (*second_uboot)(void);
 413
 414         /* Clear the BSS */
 415         memset(__bss_start, 0, __bss_end - __bss_start);
 416
 417         get_clocks();
 418
 419 #if defined(CONFIG_DEEP_SLEEP)
 420         if (is_warm_boot())
 421                 fsl_dp_disable_console();
 422 #endif
 423
 424         preloader_console_init();
 425
 426         timer_init();
 427         dram_init();
 428
 429         /* Allow OCRAM access permission as R/W */
 430 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 431         enable_layerscape_ns_access();
 432 #endif
 433
 434         /*
 435          * if it is woken up from deep sleep, then jump to second
 436          * stage uboot and continue executing without recopying
 437          * it from SD since it has already been reserved in memeory
 438          * in last boot.
 439          */
 440         if (is_warm_boot()) {
 441                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 442                 second_uboot();
 443         }
 444
 445         board_init_r(NULL, 0);
 446 }
 447 #endif
 448
 449 #ifdef CONFIG_DEEP_SLEEP
 450 /* program the regulator (MC34VR500) to support deep sleep */
 451 void ls1twr_program_regulator(void)
 452 {
 453         u8 i2c_device_id;
 454
 455 #define LS1TWR_I2C_BUS_MC34VR500        1
 456 #define MC34VR500_ADDR                  0x8
 457 #define MC34VR500_DEVICEID              0x4
 458 #define MC34VR500_DEVICEID_MASK         0x0f
 459 #ifdef CONFIG_DM_I2C
 460         struct udevice *dev;
 461         int ret;
 462
 463         ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
 464                                       1, &dev);
 465         if (ret) {
 466                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 467                        LS1TWR_I2C_BUS_MC34VR500);
 468                 return;
 469         }
 470         i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
 471                                         MC34VR500_DEVICEID_MASK;
 472         if (i2c_device_id != MC34VR500_DEVICEID) {
 473                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 474                 return;
 475         }
 476
 477         dm_i2c_reg_write(dev, 0x31, 0x4);
 478         dm_i2c_reg_write(dev, 0x4d, 0x4);
 479         dm_i2c_reg_write(dev, 0x6d, 0x38);
 480         dm_i2c_reg_write(dev, 0x6f, 0x37);
 481         dm_i2c_reg_write(dev, 0x71, 0x30);
 482 #else
 483         unsigned int i2c_bus;
 484         i2c_bus = i2c_get_bus_num();
 485         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 486         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
 487                                         MC34VR500_DEVICEID_MASK;
 488         if (i2c_device_id != MC34VR500_DEVICEID) {
 489                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 490                 return;
 491         }
 492
 493         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
 494         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
 495         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
 496         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
 497         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 498
 499         i2c_set_bus_num(i2c_bus);
 500 #endif
 501 }
 502 #endif
 503
 504 int board_init(void)
 505 {
 506 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 507         erratum_a010315();
 508 #endif
 509
 510 #ifndef CONFIG_SYS_FSL_NO_SERDES
 511         fsl_serdes_init();
 512 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 513         config_serdes_mux();
 514 #endif
 515 #endif
 516
 517         ls102xa_smmu_stream_id_init();
 518
 519 #ifdef CONFIG_U_QE
 520         u_qe_init();
 521 #endif
 522
 523 #ifdef CONFIG_DEEP_SLEEP
 524         ls1twr_program_regulator();
 525 #endif
 526         return 0;
 527 }
 528
 529 #if defined(CONFIG_SPL_BUILD)
 530 void spl_board_init(void)
 531 {
 532         ls102xa_smmu_stream_id_init();
 533 }
 534 #endif
 535
 536 #ifdef CONFIG_BOARD_LATE_INIT
 537 int board_late_init(void)
 538 {
 539 #ifdef CONFIG_CHAIN_OF_TRUST
 540         fsl_setenv_chain_of_trust();
 541 #endif
 542
 543         return 0;
 544 }
 545 #endif
 546
 547 #if defined(CONFIG_MISC_INIT_R)
 548 int misc_init_r(void)
 549 {
 550 #ifdef CONFIG_FSL_DEVICE_DISABLE
 551         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 552 #endif
 553 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 554         config_board_mux();
 555 #endif
 556
 557 #ifdef CONFIG_FSL_CAAM
 558         return sec_init();
 559 #endif
 560 }
 561 #endif
 562
 563 #if defined(CONFIG_DEEP_SLEEP)
 564 void board_sleep_prepare(void)
 565 {
 566 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 567         enable_layerscape_ns_access();
 568 #endif
 569 }
 570 #endif
 571
 572 int ft_board_setup(void *blob, bd_t *bd)
 573 {
 574         ft_cpu_setup(blob, bd);
 575
 576 #ifdef CONFIG_PCI
 577         ft_pci_setup(blob, bd);
 578 #endif
 579
 580         return 0;
 581 }
 582
 583 u8 flash_read8(void *addr)
 584 {
 585         return __raw_readb(addr + 1);
 586 }
 587
 588 void flash_write16(u16 val, void *addr)
 589 {
 590         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 591
 592         __raw_writew(shftval, addr);
 593 }
 594
 595 u16 flash_read16(void *addr)
 596 {
 597         u16 val = __raw_readw(addr);
 598
 599         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 600 }
 601
 602 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
 603         && !defined(CONFIG_SPL_BUILD)
 604 static void convert_flash_bank(char bank)
 605 {
 606         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 607
 608         printf("Now switch to boot from flash bank %d.\n", bank);
 609         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 610         cpld_data->vbank = bank;
 611
 612         printf("Reset board to enable configuration.\n");
 613         cpld_data->system_rst = CONFIG_RESET;
 614 }
 615
 616 static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 617                           char *const argv[])
 618 {
 619         if (argc != 2)
 620                 return CMD_RET_USAGE;
 621         if (strcmp(argv[1], "0") == 0)
 622                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 623         else if (strcmp(argv[1], "1") == 0)
 624                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 625         else
 626                 return CMD_RET_USAGE;
 627
 628         return 0;
 629 }
 630
 631 U_BOOT_CMD(
 632         boot_bank, 2, 0, flash_bank_cmd,
 633         "Flash bank Selection Control",
 634         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 635 );
 636
 637 static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 638                           char *const argv[])
 639 {
 640         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 641
 642         if (argc > 2)
 643                 return CMD_RET_USAGE;
 644         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 645                 cpld_data->system_rst = CONFIG_RESET;
 646         else if (strcmp(argv[1], "init") == 0)
 647                 cpld_data->global_rst = INIT_RESET;
 648         else
 649                 return CMD_RET_USAGE;
 650
 651         return 0;
 652 }
 653
 654 U_BOOT_CMD(
 655         cpld_reset, 2, 0, cpld_reset_cmd,
 656         "Reset via CPLD",
 657         "conf\n"
 658         "       -reset with current CPLD configuration\n"
 659         "init\n"
 660         "       -reset and initial CPLD configuration with default value"
 661
 662 );
 663
 664 static void print_serdes_mux(void)
 665 {
 666         char current_serdes;
 667         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 668
 669         current_serdes = cpld_data->serdes_mux;
 670
 671         printf("Serdes Lane B: ");
 672         if ((current_serdes & MASK_LANE_B) == 0)
 673                 printf("SATA,\n");
 674         else
 675                 printf("SGMII 1,\n");
 676
 677         printf("Serdes Lane C: ");
 678         if ((current_serdes & MASK_LANE_C) == 0)
 679                 printf("SGMII 1,\n");
 680         else
 681                 printf("PCIe,\n");
 682
 683         printf("Serdes Lane D: ");
 684         if ((current_serdes & MASK_LANE_D) == 0)
 685                 printf("PCIe,\n");
 686         else
 687                 printf("SGMII 2,\n");
 688
 689         printf("SGMII 1 is on lane ");
 690         if ((current_serdes & MASK_SGMII) == 0)
 691                 printf("C.\n");
 692         else
 693                 printf("B.\n");
 694 }
 695
 696 static int serdes_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 697                           char *const argv[])
 698 {
 699         if (argc != 2)
 700                 return CMD_RET_USAGE;
 701         if (strcmp(argv[1], "sata") == 0) {
 702                 printf("Set serdes lane B to SATA.\n");
 703                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 704         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 705                 printf("Set serdes lane B to SGMII 1.\n");
 706                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 707         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 708                 printf("Set serdes lane C to SGMII 1.\n");
 709                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 710         } else if (strcmp(argv[1], "sgmii2") == 0) {
 711                 printf("Set serdes lane D to SGMII 2.\n");
 712                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 713         } else if (strcmp(argv[1], "pciex1") == 0) {
 714                 printf("Set serdes lane C to PCIe X1.\n");
 715                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 716         } else if (strcmp(argv[1], "pciex2") == 0) {
 717                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 718                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 719         } else if (strcmp(argv[1], "show") == 0) {
 720                 print_serdes_mux();
 721         } else {
 722                 return CMD_RET_USAGE;
 723         }
 724
 725         return 0;
 726 }
 727
 728 U_BOOT_CMD(
 729         lane_bank, 2, 0, serdes_mux_cmd,
 730         "Multiplexed function setting for SerDes Lanes",
 731         "sata\n"
 732         "       -change lane B to sata\n"
 733         "lane_bank sgmii1b\n"
 734         "       -change lane B to SGMII1\n"
 735         "lane_bank sgmii1c\n"
 736         "       -change lane C to SGMII1\n"
 737         "lane_bank sgmii2\n"
 738         "       -change lane D to SGMII2\n"
 739         "lane_bank pciex1\n"
 740         "       -change lane C to PCIeX1\n"
 741         "lane_bank pciex2\n"
 742         "       -change lane C & lane D to PCIeX2\n"
 743         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 744 );
 745 #endif