board/freescale/ls1021atwr/ls1021atwr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <fdt_support.h>
   9 #include <i2c.h>
  10 #include <init.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/immap_ls102xa.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/fsl_serdes.h>
  15 #include <asm/arch/ls102xa_devdis.h>
  16 #include <asm/arch/ls102xa_soc.h>
  17 #include <hwconfig.h>
  18 #include <mmc.h>
  19 #include <fsl_csu.h>
  20 #include <fsl_ifc.h>
  21 #include <fsl_immap.h>
  22 #include <netdev.h>
  23 #include <fsl_mdio.h>
  24 #include <tsec.h>
  25 #include <fsl_sec.h>
  26 #include <fsl_devdis.h>
  27 #include <spl.h>
  28 #include "../common/sleep.h"
  29 #ifdef CONFIG_U_QE
  30 #include <fsl_qe.h>
  31 #endif
  32 #include <fsl_validate.h>
  33
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define VERSION_MASK            0x00FF
  38 #define BANK_MASK               0x0001
  39 #define CONFIG_RESET            0x1
  40 #define INIT_RESET              0x1
  41
  42 #define CPLD_SET_MUX_SERDES     0x20
  43 #define CPLD_SET_BOOT_BANK      0x40
  44
  45 #define BOOT_FROM_UPPER_BANK    0x0
  46 #define BOOT_FROM_LOWER_BANK    0x1
  47
  48 #define LANEB_SATA              (0x01)
  49 #define LANEB_SGMII1            (0x02)
  50 #define LANEC_SGMII1            (0x04)
  51 #define LANEC_PCIEX1            (0x08)
  52 #define LANED_PCIEX2            (0x10)
  53 #define LANED_SGMII2            (0x20)
  54
  55 #define MASK_LANE_B             0x1
  56 #define MASK_LANE_C             0x2
  57 #define MASK_LANE_D             0x4
  58 #define MASK_SGMII              0x8
  59
  60 #define KEEP_STATUS             0x0
  61 #define NEED_RESET              0x1
  62
  63 #define SOFT_MUX_ON_I2C3_IFC    0x2
  64 #define SOFT_MUX_ON_CAN3_USB2   0x8
  65 #define SOFT_MUX_ON_QE_LCD      0x10
  66
  67 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  68 #define PIN_I2C3_IFC_MUX_IFC    0x1
  69 #define PIN_CAN3_USB2_MUX_USB2  0x0
  70 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  71 #define PIN_QE_LCD_MUX_LCD      0x0
  72 #define PIN_QE_LCD_MUX_QE       0x1
  73
  74 struct cpld_data {
  75         u8 cpld_ver;            /* cpld revision */
  76         u8 cpld_ver_sub;        /* cpld sub revision */
  77         u8 pcba_ver;            /* pcb revision number */
  78         u8 system_rst;          /* reset system by cpld */
  79         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  80         u8 cfg_rcw_src1;        /* Reset config word 1 */
  81         u8 cfg_rcw_src2;        /* Reset config word 2 */
  82         u8 vbank;               /* Flash bank selection Control */
  83         u8 gpio;                /* GPIO for TWR-ELEV */
  84         u8 i2c3_ifc_mux;
  85         u8 mux_spi2;
  86         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  87         u8 qe_lcd_mux;          /* QE and LCD Selection */
  88         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  89         u8 global_rst;          /* reset with init CPLD reg to default */
  90         u8 rev1;                /* Reserved */
  91         u8 rev2;                /* Reserved */
  92 };
  93
  94 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  95 static void cpld_show(void)
  96 {
  97         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  98
  99         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
 100                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
 101                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 102                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 103                in_8(&cpld_data->vbank) & BANK_MASK);
 104
 105 #ifdef CONFIG_DEBUG
 106         printf("soft_mux_on =%x\n",
 107                in_8(&cpld_data->soft_mux_on));
 108         printf("cfg_rcw_src1 =%x\n",
 109                in_8(&cpld_data->cfg_rcw_src1));
 110         printf("cfg_rcw_src2 =%x\n",
 111                in_8(&cpld_data->cfg_rcw_src2));
 112         printf("vbank =%x\n",
 113                in_8(&cpld_data->vbank));
 114         printf("gpio =%x\n",
 115                in_8(&cpld_data->gpio));
 116         printf("i2c3_ifc_mux =%x\n",
 117                in_8(&cpld_data->i2c3_ifc_mux));
 118         printf("mux_spi2 =%x\n",
 119                in_8(&cpld_data->mux_spi2));
 120         printf("can3_usb2_mux =%x\n",
 121                in_8(&cpld_data->can3_usb2_mux));
 122         printf("qe_lcd_mux =%x\n",
 123                in_8(&cpld_data->qe_lcd_mux));
 124         printf("serdes_mux =%x\n",
 125                in_8(&cpld_data->serdes_mux));
 126 #endif
 127 }
 128 #endif
 129
 130 int checkboard(void)
 131 {
 132         puts("Board: LS1021ATWR\n");
 133 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 134         cpld_show();
 135 #endif
 136
 137         return 0;
 138 }
 139
 140 void ddrmc_init(void)
 141 {
 142         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 143         u32 temp_sdram_cfg, tmp;
 144
 145         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 146
 147         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 148         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 149
 150         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 151         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 152         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 153         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 154         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 155         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 156
 157 #ifdef CONFIG_DEEP_SLEEP
 158         if (is_warm_boot()) {
 159                 out_be32(&ddr->sdram_cfg_2,
 160                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 161                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 162                 out_be32(&ddr->init_ext_addr, (1 << 31));
 163
 164                 /* DRAM VRef will not be trained */
 165                 out_be32(&ddr->ddr_cdr2,
 166                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 167         } else
 168 #endif
 169         {
 170                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 171                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 172         }
 173
 174         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 175         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 176
 177         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 178
 179         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 180
 181         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 182         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 183
 184         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 185
 186         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 187         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 188
 189         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 190
 191         /* DDR erratum A-009942 */
 192         tmp = in_be32(&ddr->debug[28]);
 193         out_be32(&ddr->debug[28], tmp | 0x0070006f);
 194
 195         udelay(1);
 196
 197 #ifdef CONFIG_DEEP_SLEEP
 198         if (is_warm_boot()) {
 199                 /* enter self-refresh */
 200                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 201                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 202                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 203
 204                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 205         } else
 206 #endif
 207                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 208
 209         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 210
 211 #ifdef CONFIG_DEEP_SLEEP
 212         if (is_warm_boot()) {
 213                 /* exit self-refresh */
 214                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 215                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 216                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 217         }
 218 #endif
 219 }
 220
 221 int dram_init(void)
 222 {
 223 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 224         ddrmc_init();
 225 #endif
 226
 227         erratum_a008850_post();
 228
 229         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 230
 231 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 232         fsl_dp_resume();
 233 #endif
 234
 235         return 0;
 236 }
 237
 238 int board_eth_init(bd_t *bis)
 239 {
 240         return pci_eth_init(bis);
 241 }
 242
 243 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 244 static void convert_serdes_mux(int type, int need_reset)
 245 {
 246         char current_serdes;
 247         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 248
 249         current_serdes = cpld_data->serdes_mux;
 250
 251         switch (type) {
 252         case LANEB_SATA:
 253                 current_serdes &= ~MASK_LANE_B;
 254                 break;
 255         case LANEB_SGMII1:
 256                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 257                 break;
 258         case LANEC_SGMII1:
 259                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 260                 break;
 261         case LANED_SGMII2:
 262                 current_serdes |= MASK_LANE_D;
 263                 break;
 264         case LANEC_PCIEX1:
 265                 current_serdes |= MASK_LANE_C;
 266                 break;
 267         case (LANED_PCIEX2 | LANEC_PCIEX1):
 268                 current_serdes |= MASK_LANE_C;
 269                 current_serdes &= ~MASK_LANE_D;
 270                 break;
 271         default:
 272                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 273                 return;
 274         }
 275
 276         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 277         cpld_data->serdes_mux = current_serdes;
 278
 279         if (need_reset == 1) {
 280                 printf("Reset board to enable configuration\n");
 281                 cpld_data->system_rst = CONFIG_RESET;
 282         }
 283 }
 284
 285 int config_serdes_mux(void)
 286 {
 287         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 288         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 289
 290         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 291         switch (protocol) {
 292         case 0x10:
 293                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 294                 convert_serdes_mux(LANED_PCIEX2 |
 295                                 LANEC_PCIEX1, KEEP_STATUS);
 296                 break;
 297         case 0x20:
 298                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 299                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 300                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 301                 break;
 302         case 0x30:
 303                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 304                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 305                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 306                 break;
 307         case 0x70:
 308                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 309                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 310                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 311                 break;
 312         }
 313
 314         return 0;
 315 }
 316 #endif
 317
 318 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 319 int config_board_mux(void)
 320 {
 321         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 322         int conflict_flag;
 323
 324         conflict_flag = 0;
 325         if (hwconfig("i2c3")) {
 326                 conflict_flag++;
 327                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 328                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 329         }
 330
 331         if (hwconfig("ifc")) {
 332                 conflict_flag++;
 333                 /* some signals can not enable simultaneous*/
 334                 if (conflict_flag > 1)
 335                         goto conflict;
 336                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 337                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 338         }
 339
 340         conflict_flag = 0;
 341         if (hwconfig("usb2")) {
 342                 conflict_flag++;
 343                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 344                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 345         }
 346
 347         if (hwconfig("can3")) {
 348                 conflict_flag++;
 349                 /* some signals can not enable simultaneous*/
 350                 if (conflict_flag > 1)
 351                         goto conflict;
 352                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 353                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 354         }
 355
 356         conflict_flag = 0;
 357         if (hwconfig("lcd")) {
 358                 conflict_flag++;
 359                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 360                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 361         }
 362
 363         if (hwconfig("qe")) {
 364                 conflict_flag++;
 365                 /* some signals can not enable simultaneous*/
 366                 if (conflict_flag > 1)
 367                         goto conflict;
 368                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 369                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 370         }
 371
 372         return 0;
 373
 374 conflict:
 375         printf("WARNING: pin conflict! MUX setting may failed!\n");
 376         return 0;
 377 }
 378 #endif
 379
 380 int board_early_init_f(void)
 381 {
 382         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 383
 384 #ifdef CONFIG_TSEC_ENET
 385         /* clear BD & FR bits for BE BD's and frame data */
 386         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 387         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 388 #endif
 389
 390 #ifdef CONFIG_FSL_IFC
 391         init_early_memctl_regs();
 392 #endif
 393
 394         arch_soc_init();
 395
 396 #if defined(CONFIG_DEEP_SLEEP)
 397         if (is_warm_boot()) {
 398                 timer_init();
 399                 dram_init();
 400         }
 401 #endif
 402
 403         return 0;
 404 }
 405
 406 #ifdef CONFIG_SPL_BUILD
 407 void board_init_f(ulong dummy)
 408 {
 409         void (*second_uboot)(void);
 410
 411         /* Clear the BSS */
 412         memset(__bss_start, 0, __bss_end - __bss_start);
 413
 414         get_clocks();
 415
 416 #if defined(CONFIG_DEEP_SLEEP)
 417         if (is_warm_boot())
 418                 fsl_dp_disable_console();
 419 #endif
 420
 421         preloader_console_init();
 422
 423         timer_init();
 424         dram_init();
 425
 426         /* Allow OCRAM access permission as R/W */
 427 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 428         enable_layerscape_ns_access();
 429 #endif
 430
 431         /*
 432          * if it is woken up from deep sleep, then jump to second
 433          * stage uboot and continue executing without recopying
 434          * it from SD since it has already been reserved in memeory
 435          * in last boot.
 436          */
 437         if (is_warm_boot()) {
 438                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 439                 second_uboot();
 440         }
 441
 442         board_init_r(NULL, 0);
 443 }
 444 #endif
 445
 446 #ifdef CONFIG_DEEP_SLEEP
 447 /* program the regulator (MC34VR500) to support deep sleep */
 448 void ls1twr_program_regulator(void)
 449 {
 450         unsigned int i2c_bus;
 451         u8 i2c_device_id;
 452
 453 #define LS1TWR_I2C_BUS_MC34VR500        1
 454 #define MC34VR500_ADDR                  0x8
 455 #define MC34VR500_DEVICEID              0x4
 456 #define MC34VR500_DEVICEID_MASK         0x0f
 457
 458         i2c_bus = i2c_get_bus_num();
 459         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 460         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
 461                                         MC34VR500_DEVICEID_MASK;
 462         if (i2c_device_id != MC34VR500_DEVICEID) {
 463                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 464                 return;
 465         }
 466
 467         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
 468         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
 469         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
 470         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
 471         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 472
 473         i2c_set_bus_num(i2c_bus);
 474 }
 475 #endif
 476
 477 int board_init(void)
 478 {
 479 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 480         erratum_a010315();
 481 #endif
 482
 483 #ifndef CONFIG_SYS_FSL_NO_SERDES
 484         fsl_serdes_init();
 485 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 486         config_serdes_mux();
 487 #endif
 488 #endif
 489
 490         ls102xa_smmu_stream_id_init();
 491
 492 #ifdef CONFIG_U_QE
 493         u_qe_init();
 494 #endif
 495
 496 #ifdef CONFIG_DEEP_SLEEP
 497         ls1twr_program_regulator();
 498 #endif
 499         return 0;
 500 }
 501
 502 #if defined(CONFIG_SPL_BUILD)
 503 void spl_board_init(void)
 504 {
 505         ls102xa_smmu_stream_id_init();
 506 }
 507 #endif
 508
 509 #ifdef CONFIG_BOARD_LATE_INIT
 510 int board_late_init(void)
 511 {
 512 #ifdef CONFIG_CHAIN_OF_TRUST
 513         fsl_setenv_chain_of_trust();
 514 #endif
 515
 516         return 0;
 517 }
 518 #endif
 519
 520 #if defined(CONFIG_MISC_INIT_R)
 521 int misc_init_r(void)
 522 {
 523 #ifdef CONFIG_FSL_DEVICE_DISABLE
 524         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 525 #endif
 526 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 527         config_board_mux();
 528 #endif
 529
 530 #ifdef CONFIG_FSL_CAAM
 531         return sec_init();
 532 #endif
 533 }
 534 #endif
 535
 536 #if defined(CONFIG_DEEP_SLEEP)
 537 void board_sleep_prepare(void)
 538 {
 539 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 540         enable_layerscape_ns_access();
 541 #endif
 542 }
 543 #endif
 544
 545 int ft_board_setup(void *blob, bd_t *bd)
 546 {
 547         ft_cpu_setup(blob, bd);
 548
 549 #ifdef CONFIG_PCI
 550         ft_pci_setup(blob, bd);
 551 #endif
 552
 553         return 0;
 554 }
 555
 556 u8 flash_read8(void *addr)
 557 {
 558         return __raw_readb(addr + 1);
 559 }
 560
 561 void flash_write16(u16 val, void *addr)
 562 {
 563         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 564
 565         __raw_writew(shftval, addr);
 566 }
 567
 568 u16 flash_read16(void *addr)
 569 {
 570         u16 val = __raw_readw(addr);
 571
 572         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 573 }
 574
 575 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
 576         && !defined(CONFIG_SPL_BUILD)
 577 static void convert_flash_bank(char bank)
 578 {
 579         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 580
 581         printf("Now switch to boot from flash bank %d.\n", bank);
 582         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 583         cpld_data->vbank = bank;
 584
 585         printf("Reset board to enable configuration.\n");
 586         cpld_data->system_rst = CONFIG_RESET;
 587 }
 588
 589 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 590                           char * const argv[])
 591 {
 592         if (argc != 2)
 593                 return CMD_RET_USAGE;
 594         if (strcmp(argv[1], "0") == 0)
 595                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 596         else if (strcmp(argv[1], "1") == 0)
 597                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 598         else
 599                 return CMD_RET_USAGE;
 600
 601         return 0;
 602 }
 603
 604 U_BOOT_CMD(
 605         boot_bank, 2, 0, flash_bank_cmd,
 606         "Flash bank Selection Control",
 607         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 608 );
 609
 610 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 611                           char * const argv[])
 612 {
 613         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 614
 615         if (argc > 2)
 616                 return CMD_RET_USAGE;
 617         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 618                 cpld_data->system_rst = CONFIG_RESET;
 619         else if (strcmp(argv[1], "init") == 0)
 620                 cpld_data->global_rst = INIT_RESET;
 621         else
 622                 return CMD_RET_USAGE;
 623
 624         return 0;
 625 }
 626
 627 U_BOOT_CMD(
 628         cpld_reset, 2, 0, cpld_reset_cmd,
 629         "Reset via CPLD",
 630         "conf\n"
 631         "       -reset with current CPLD configuration\n"
 632         "init\n"
 633         "       -reset and initial CPLD configuration with default value"
 634
 635 );
 636
 637 static void print_serdes_mux(void)
 638 {
 639         char current_serdes;
 640         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 641
 642         current_serdes = cpld_data->serdes_mux;
 643
 644         printf("Serdes Lane B: ");
 645         if ((current_serdes & MASK_LANE_B) == 0)
 646                 printf("SATA,\n");
 647         else
 648                 printf("SGMII 1,\n");
 649
 650         printf("Serdes Lane C: ");
 651         if ((current_serdes & MASK_LANE_C) == 0)
 652                 printf("SGMII 1,\n");
 653         else
 654                 printf("PCIe,\n");
 655
 656         printf("Serdes Lane D: ");
 657         if ((current_serdes & MASK_LANE_D) == 0)
 658                 printf("PCIe,\n");
 659         else
 660                 printf("SGMII 2,\n");
 661
 662         printf("SGMII 1 is on lane ");
 663         if ((current_serdes & MASK_SGMII) == 0)
 664                 printf("C.\n");
 665         else
 666                 printf("B.\n");
 667 }
 668
 669 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 670                           char * const argv[])
 671 {
 672         if (argc != 2)
 673                 return CMD_RET_USAGE;
 674         if (strcmp(argv[1], "sata") == 0) {
 675                 printf("Set serdes lane B to SATA.\n");
 676                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 677         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 678                 printf("Set serdes lane B to SGMII 1.\n");
 679                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 680         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 681                 printf("Set serdes lane C to SGMII 1.\n");
 682                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 683         } else if (strcmp(argv[1], "sgmii2") == 0) {
 684                 printf("Set serdes lane D to SGMII 2.\n");
 685                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 686         } else if (strcmp(argv[1], "pciex1") == 0) {
 687                 printf("Set serdes lane C to PCIe X1.\n");
 688                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 689         } else if (strcmp(argv[1], "pciex2") == 0) {
 690                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 691                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 692         } else if (strcmp(argv[1], "show") == 0) {
 693                 print_serdes_mux();
 694         } else {
 695                 return CMD_RET_USAGE;
 696         }
 697
 698         return 0;
 699 }
 700
 701 U_BOOT_CMD(
 702         lane_bank, 2, 0, serdes_mux_cmd,
 703         "Multiplexed function setting for SerDes Lanes",
 704         "sata\n"
 705         "       -change lane B to sata\n"
 706         "lane_bank sgmii1b\n"
 707         "       -change lane B to SGMII1\n"
 708         "lane_bank sgmii1c\n"
 709         "       -change lane C to SGMII1\n"
 710         "lane_bank sgmii2\n"
 711         "       -change lane D to SGMII2\n"
 712         "lane_bank pciex1\n"
 713         "       -change lane C to PCIeX1\n"
 714         "lane_bank pciex2\n"
 715         "       -change lane C & lane D to PCIeX2\n"
 716         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 717 );
 718 #endif