board/freescale/ls1021atsn/ls1021atsn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright 2016-2019 NXP Semiconductors
   3  */
   4 #include <common.h>
   5 #include <clock_legacy.h>
   6 #include <fdt_support.h>
   7 #include <init.h>
   8 #include <net.h>
   9 #include <asm/arch-ls102xa/ls102xa_soc.h>
  10 #include <asm/arch/ls102xa_devdis.h>
  11 #include <asm/arch/immap_ls102xa.h>
  12 #include <asm/arch/ls102xa_soc.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <linux/delay.h>
  15 #include "../common/sleep.h"
  16 #include <fsl_validate.h>
  17 #include <fsl_immap.h>
  18 #include <fsl_csu.h>
  19 #include <netdev.h>
  20 #include <spl.h>
  21 #ifdef CONFIG_U_QE
  22 #include <fsl_qe.h>
  23 #endif
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 static void ddrmc_init(void)
  28 {
  29 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  30         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  31         u32 temp_sdram_cfg, tmp;
  32
  33         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  34
  35         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  36         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  37
  38         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  39         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  40         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  41         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  42         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  43         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  44
  45 #ifdef CONFIG_DEEP_SLEEP
  46         if (is_warm_boot()) {
  47                 out_be32(&ddr->sdram_cfg_2,
  48                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  49                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  50                 out_be32(&ddr->init_ext_addr, (1 << 31));
  51
  52                 /* DRAM VRef will not be trained */
  53                 out_be32(&ddr->ddr_cdr2,
  54                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  55         } else
  56 #endif
  57         {
  58                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  59                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  60         }
  61
  62         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  63         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  64
  65         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  66
  67         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  68
  69         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  70         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  71
  72         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  73
  74         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  75         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  76
  77         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  78
  79         /* DDR erratum A-009942 */
  80         tmp = in_be32(&ddr->debug[28]);
  81         out_be32(&ddr->debug[28], tmp | 0x0070006f);
  82
  83         udelay(1);
  84
  85 #ifdef CONFIG_DEEP_SLEEP
  86         if (is_warm_boot()) {
  87                 /* enter self-refresh */
  88                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  89                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  90                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  91
  92                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  93         } else
  94 #endif
  95                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  96
  97         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  98
  99 #ifdef CONFIG_DEEP_SLEEP
 100         if (is_warm_boot()) {
 101                 /* exit self-refresh */
 102                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 103                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 104                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 105         }
 106 #endif
 107 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
 108 }
 109
 110 int dram_init(void)
 111 {
 112         ddrmc_init();
 113
 114         erratum_a008850_post();
 115
 116         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 117
 118 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 119         fsl_dp_resume();
 120 #endif
 121
 122         return 0;
 123 }
 124
 125 int board_eth_init(bd_t *bis)
 126 {
 127         return pci_eth_init(bis);
 128 }
 129
 130 int board_early_init_f(void)
 131 {
 132         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 133
 134 #ifdef CONFIG_TSEC_ENET
 135         /*
 136          * Clear BD & FR bits for big endian BD's and frame data (aka set
 137          * correct eTSEC endianness). This is crucial in ensuring that it does
 138          * not report Data Parity Errors in its RX/TX FIFOs when attempting to
 139          * send traffic.
 140          */
 141         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 142         /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
 143         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 144 #endif
 145
 146         arch_soc_init();
 147
 148 #if defined(CONFIG_DEEP_SLEEP)
 149         if (is_warm_boot()) {
 150                 timer_init();
 151                 dram_init();
 152         }
 153 #endif
 154
 155         return 0;
 156 }
 157
 158 #ifdef CONFIG_SPL_BUILD
 159 void board_init_f(ulong dummy)
 160 {
 161         void (*second_uboot)(void);
 162
 163         /* Clear the BSS */
 164         memset(__bss_start, 0, __bss_end - __bss_start);
 165
 166         get_clocks();
 167
 168 #if defined(CONFIG_DEEP_SLEEP)
 169         if (is_warm_boot())
 170                 fsl_dp_disable_console();
 171 #endif
 172
 173         preloader_console_init();
 174
 175         dram_init();
 176
 177         /* Allow OCRAM access permission as R/W */
 178 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 179         enable_layerscape_ns_access();
 180         enable_layerscape_ns_access();
 181 #endif
 182
 183         /*
 184          * if it is woken up from deep sleep, then jump to second
 185          * stage U-Boot and continue executing without recopying
 186          * it from SD since it has already been reserved in memory
 187          * in last boot.
 188          */
 189         if (is_warm_boot()) {
 190                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 191                 second_uboot();
 192         }
 193
 194         board_init_r(NULL, 0);
 195 }
 196 #endif
 197
 198 int board_init(void)
 199 {
 200 #ifndef CONFIG_SYS_FSL_NO_SERDES
 201         fsl_serdes_init();
 202 #endif
 203         ls102xa_smmu_stream_id_init();
 204
 205 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 206         enable_layerscape_ns_access();
 207 #endif
 208
 209 #ifdef CONFIG_U_QE
 210         u_qe_init();
 211 #endif
 212
 213         return 0;
 214 }
 215
 216 #if defined(CONFIG_SPL_BUILD)
 217 void spl_board_init(void)
 218 {
 219         ls102xa_smmu_stream_id_init();
 220 }
 221 #endif
 222
 223 #ifdef CONFIG_BOARD_LATE_INIT
 224 int board_late_init(void)
 225 {
 226 #ifdef CONFIG_CHAIN_OF_TRUST
 227         fsl_setenv_chain_of_trust();
 228 #endif
 229
 230         return 0;
 231 }
 232 #endif
 233
 234 #if defined(CONFIG_MISC_INIT_R)
 235 int misc_init_r(void)
 236 {
 237 #ifdef CONFIG_FSL_DEVICE_DISABLE
 238         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 239 #endif
 240
 241 #ifdef CONFIG_FSL_CAAM
 242         return sec_init();
 243 #endif
 244 }
 245 #endif
 246
 247 #if defined(CONFIG_DEEP_SLEEP)
 248 void board_sleep_prepare(void)
 249 {
 250 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 251         enable_layerscape_ns_access();
 252 #endif
 253 }
 254 #endif
 255
 256 int ft_board_setup(void *blob, bd_t *bd)
 257 {
 258         ft_cpu_setup(blob, bd);
 259
 260 #ifdef CONFIG_PCI
 261         ft_pci_setup(blob, bd);
 262 #endif
 263
 264         return 0;
 265 }