board/freescale/ls1021aqds/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <fsl_ddr_sdram.h>
   8 #include <fsl_ddr_dimm_params.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <linux/delay.h>
  14 #include "ddr.h"
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 void fsl_ddr_board_options(memctl_options_t *popts,
  19                            dimm_params_t *pdimm,
  20                            unsigned int ctrl_num)
  21 {
  22         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  23         ulong ddr_freq;
  24
  25         if (ctrl_num > 3) {
  26                 printf("Not supported controller number %d\n", ctrl_num);
  27                 return;
  28         }
  29         if (!pdimm->n_ranks)
  30                 return;
  31
  32         pbsp = udimms[0];
  33
  34         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  35          * freqency and n_banks specified in board_specific_parameters table.
  36          */
  37         ddr_freq = get_ddr_freq(0) / 1000000;
  38         while (pbsp->datarate_mhz_high) {
  39                 if (pbsp->n_ranks == pdimm->n_ranks) {
  40                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  41                                 popts->clk_adjust = pbsp->clk_adjust;
  42                                 popts->wrlvl_start = pbsp->wrlvl_start;
  43                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  44                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  45                                 popts->cpo_override = pbsp->cpo_override;
  46                                 popts->write_data_delay =
  47                                         pbsp->write_data_delay;
  48                                 goto found;
  49                         }
  50                         pbsp_highest = pbsp;
  51                 }
  52                 pbsp++;
  53         }
  54
  55         if (pbsp_highest) {
  56                 printf("Error: board specific timing not found for %lu MT/s\n",
  57                        ddr_freq);
  58                 printf("Trying to use the highest speed (%u) parameters\n",
  59                        pbsp_highest->datarate_mhz_high);
  60                 popts->clk_adjust = pbsp_highest->clk_adjust;
  61                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  62                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  63                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  64         } else {
  65                 panic("DIMM is not supported by this board");
  66         }
  67 found:
  68         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  69               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  70
  71         /* force DDR bus width to 32 bits */
  72         popts->data_bus_width = 1;
  73         popts->otf_burst_chop_en = 0;
  74         popts->burst_length = DDR_BL8;
  75
  76         /*
  77          * Factors to consider for half-strength driver enable:
  78          *      - number of DIMMs installed
  79          */
  80         popts->half_strength_driver_enable = 1;
  81         /*
  82          * Write leveling override
  83          */
  84         popts->wrlvl_override = 1;
  85         popts->wrlvl_sample = 0xf;
  86
  87         /*
  88          * Rtt and Rtt_WR override
  89          */
  90         popts->rtt_override = 0;
  91
  92         /* Enable ZQ calibration */
  93         popts->zq_en = 1;
  94
  95 #ifdef CONFIG_SYS_FSL_DDR4
  96         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  97         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  98                           DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
  99 #else
 100         popts->cswl_override = DDR_CSWL_CS0;
 101
 102         /* optimize cpo for erratum A-009942 */
 103         popts->cpo_sample = 0x58;
 104
 105         /* DHC_EN =1, ODT = 75 Ohm */
 106         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 107         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 108 #endif
 109 }
 110
 111 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 112 dimm_params_t ddr_raw_timing = {
 113         .n_ranks = 1,
 114         .rank_density = 1073741824u,
 115         .capacity = 1073741824u,
 116         .primary_sdram_width = 32,
 117         .ec_sdram_width = 0,
 118         .registered_dimm = 0,
 119         .mirrored_dimm = 0,
 120         .n_row_addr = 15,
 121         .n_col_addr = 10,
 122         .n_banks_per_sdram_device = 8,
 123         .edc_config = 0,
 124         .burst_lengths_bitmask = 0x0c,
 125
 126         .tckmin_x_ps = 1071,
 127         .caslat_x = 0xfe << 4,  /* 5,6,7,8 */
 128         .taa_ps = 13125,
 129         .twr_ps = 15000,
 130         .trcd_ps = 13125,
 131         .trrd_ps = 7500,
 132         .trp_ps = 13125,
 133         .tras_ps = 37500,
 134         .trc_ps = 50625,
 135         .trfc_ps = 160000,
 136         .twtr_ps = 7500,
 137         .trtp_ps = 7500,
 138         .refresh_rate_ps = 7800000,
 139         .tfaw_ps = 37500,
 140 };
 141
 142 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 143                             unsigned int controller_number,
 144                             unsigned int dimm_number)
 145 {
 146         static const char dimm_model[] = "Fixed DDR on board";
 147
 148         if (((controller_number == 0) && (dimm_number == 0)) ||
 149             ((controller_number == 1) && (dimm_number == 0))) {
 150                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 151                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 152                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 153         }
 154
 155         return 0;
 156 }
 157 #endif
 158
 159 #if defined(CONFIG_DEEP_SLEEP)
 160 void board_mem_sleep_setup(void)
 161 {
 162         void __iomem *qixis_base = (void *)QIXIS_BASE;
 163
 164         /* does not provide HW signals for power management */
 165         clrbits_8(qixis_base + 0x21, 0x2);
 166         udelay(1);
 167 }
 168 #endif
 169
 170 int fsl_initdram(void)
 171 {
 172         phys_size_t dram_size;
 173
 174 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
 175         puts("Initializing DDR....using SPD\n");
 176         dram_size = fsl_ddr_sdram();
 177 #else
 178         dram_size =  fsl_ddr_sdram_size();
 179 #endif
 180
 181 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 182         fsl_dp_resume();
 183 #endif
 184
 185         erratum_a008850_post();
 186
 187         gd->ram_size = dram_size;
 188
 189         return 0;
 190 }
 191
 192 int dram_init_banksize(void)
 193 {
 194         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 195         gd->bd->bi_dram[0].size = gd->ram_size;
 196
 197         return 0;
 198 }