board/freescale/ls1021aqds/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <fsl_ddr_sdram.h>
   8 #include <fsl_ddr_dimm_params.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include "ddr.h"
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 void fsl_ddr_board_options(memctl_options_t *popts,
  18                            dimm_params_t *pdimm,
  19                            unsigned int ctrl_num)
  20 {
  21         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  22         ulong ddr_freq;
  23
  24         if (ctrl_num > 3) {
  25                 printf("Not supported controller number %d\n", ctrl_num);
  26                 return;
  27         }
  28         if (!pdimm->n_ranks)
  29                 return;
  30
  31         pbsp = udimms[0];
  32
  33         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  34          * freqency and n_banks specified in board_specific_parameters table.
  35          */
  36         ddr_freq = get_ddr_freq(0) / 1000000;
  37         while (pbsp->datarate_mhz_high) {
  38                 if (pbsp->n_ranks == pdimm->n_ranks) {
  39                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  40                                 popts->clk_adjust = pbsp->clk_adjust;
  41                                 popts->wrlvl_start = pbsp->wrlvl_start;
  42                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  43                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  44                                 popts->cpo_override = pbsp->cpo_override;
  45                                 popts->write_data_delay =
  46                                         pbsp->write_data_delay;
  47                                 goto found;
  48                         }
  49                         pbsp_highest = pbsp;
  50                 }
  51                 pbsp++;
  52         }
  53
  54         if (pbsp_highest) {
  55                 printf("Error: board specific timing not found for %lu MT/s\n",
  56                        ddr_freq);
  57                 printf("Trying to use the highest speed (%u) parameters\n",
  58                        pbsp_highest->datarate_mhz_high);
  59                 popts->clk_adjust = pbsp_highest->clk_adjust;
  60                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  61                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  62                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  63         } else {
  64                 panic("DIMM is not supported by this board");
  65         }
  66 found:
  67         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  68               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  69
  70         /* force DDR bus width to 32 bits */
  71         popts->data_bus_width = 1;
  72         popts->otf_burst_chop_en = 0;
  73         popts->burst_length = DDR_BL8;
  74
  75         /*
  76          * Factors to consider for half-strength driver enable:
  77          *      - number of DIMMs installed
  78          */
  79         popts->half_strength_driver_enable = 1;
  80         /*
  81          * Write leveling override
  82          */
  83         popts->wrlvl_override = 1;
  84         popts->wrlvl_sample = 0xf;
  85
  86         /*
  87          * Rtt and Rtt_WR override
  88          */
  89         popts->rtt_override = 0;
  90
  91         /* Enable ZQ calibration */
  92         popts->zq_en = 1;
  93
  94 #ifdef CONFIG_SYS_FSL_DDR4
  95         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  96         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  97                           DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
  98 #else
  99         popts->cswl_override = DDR_CSWL_CS0;
 100
 101         /* optimize cpo for erratum A-009942 */
 102         popts->cpo_sample = 0x58;
 103
 104         /* DHC_EN =1, ODT = 75 Ohm */
 105         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 106         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 107 #endif
 108 }
 109
 110 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 111 dimm_params_t ddr_raw_timing = {
 112         .n_ranks = 1,
 113         .rank_density = 1073741824u,
 114         .capacity = 1073741824u,
 115         .primary_sdram_width = 32,
 116         .ec_sdram_width = 0,
 117         .registered_dimm = 0,
 118         .mirrored_dimm = 0,
 119         .n_row_addr = 15,
 120         .n_col_addr = 10,
 121         .n_banks_per_sdram_device = 8,
 122         .edc_config = 0,
 123         .burst_lengths_bitmask = 0x0c,
 124
 125         .tckmin_x_ps = 1071,
 126         .caslat_x = 0xfe << 4,  /* 5,6,7,8 */
 127         .taa_ps = 13125,
 128         .twr_ps = 15000,
 129         .trcd_ps = 13125,
 130         .trrd_ps = 7500,
 131         .trp_ps = 13125,
 132         .tras_ps = 37500,
 133         .trc_ps = 50625,
 134         .trfc_ps = 160000,
 135         .twtr_ps = 7500,
 136         .trtp_ps = 7500,
 137         .refresh_rate_ps = 7800000,
 138         .tfaw_ps = 37500,
 139 };
 140
 141 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 142                             unsigned int controller_number,
 143                             unsigned int dimm_number)
 144 {
 145         static const char dimm_model[] = "Fixed DDR on board";
 146
 147         if (((controller_number == 0) && (dimm_number == 0)) ||
 148             ((controller_number == 1) && (dimm_number == 0))) {
 149                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 150                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 151                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 152         }
 153
 154         return 0;
 155 }
 156 #endif
 157
 158 #if defined(CONFIG_DEEP_SLEEP)
 159 void board_mem_sleep_setup(void)
 160 {
 161         void __iomem *qixis_base = (void *)QIXIS_BASE;
 162
 163         /* does not provide HW signals for power management */
 164         clrbits_8(qixis_base + 0x21, 0x2);
 165         udelay(1);
 166 }
 167 #endif
 168
 169 int fsl_initdram(void)
 170 {
 171         phys_size_t dram_size;
 172
 173 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
 174         puts("Initializing DDR....using SPD\n");
 175         dram_size = fsl_ddr_sdram();
 176 #else
 177         dram_size =  fsl_ddr_sdram_size();
 178 #endif
 179
 180 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 181         fsl_dp_resume();
 182 #endif
 183
 184         erratum_a008850_post();
 185
 186         gd->ram_size = dram_size;
 187
 188         return 0;
 189 }
 190
 191 int dram_init_banksize(void)
 192 {
 193         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 194         gd->bd->bi_dram[0].size = gd->ram_size;
 195
 196         return 0;
 197 }