1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
7 #include <fdt_support.h>
10 #include <asm/cache.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #ifdef CONFIG_FSL_LS_PPA
15 #include <asm/arch/ppa.h>
17 #include <asm/arch/mmu.h>
18 #include <asm/arch/soc.h>
23 #include <fsl_esdhc.h>
24 #include <env_internal.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define BOOT_FROM_UPPER_BANK 0x2
32 #define BOOT_FROM_LOWER_BANK 0x1
36 #ifdef CONFIG_TARGET_LS1012ARDB
40 puts("Board: LS1012ARDB ");
42 /* Initialize i2c early for Serial flash bank information */
43 #if defined(CONFIG_DM_I2C)
46 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
49 printf("%s: Cannot find udev for a bus %d\n", __func__,
53 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
54 #else /* Non DM I2C support - will be removed */
55 i2c_set_bus_num(bus_num);
56 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
59 printf("Error reading i2c boot information!\n");
60 return 0; /* Don't want to hang() on this error */
64 switch (in1 & SW_REV_MASK) {
91 printf(", boot from QSPI");
92 if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
94 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
96 else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
102 puts("Board: LS1012A2G5RDB ");
107 #ifdef CONFIG_TFABOOT
110 gd->ram_size = tfa_get_dram_size();
112 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
119 #ifndef CONFIG_TFABOOT
120 static const struct fsl_mmdc_info mparam = {
121 0x05180000, /* mdctl */
122 0x00030035, /* mdpdc */
123 0x12554000, /* mdotc */
124 0xbabf7954, /* mdcfg0 */
125 0xdb328f64, /* mdcfg1 */
126 0x01ff00db, /* mdcfg2 */
127 0x00001680, /* mdmisc */
128 0x0f3c8000, /* mdref */
129 0x00002000, /* mdrwd */
130 0x00bf1023, /* mdor */
131 0x0000003f, /* mdasp */
132 0x0000022a, /* mpodtctrl */
133 0xa1390003, /* mpzqhwctrl */
139 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
140 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
141 /* This will break-before-make MMU for DDR */
142 update_early_mmu_table();
150 int board_early_init_f(void)
152 fsl_lsch2_early_init_f();
159 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
160 CONFIG_SYS_CCI400_OFFSET);
162 * Set CCI-400 control override register to enable barrier
165 if (current_el() == 3)
166 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
168 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
172 #ifdef CONFIG_ENV_IS_NOWHERE
173 gd->env_addr = (ulong)&default_environment[0];
176 #ifdef CONFIG_FSL_CAAM
180 #ifdef CONFIG_FSL_LS_PPA
186 #ifdef CONFIG_TARGET_LS1012ARDB
187 int esdhc_status_fixup(void *blob, const char *compat)
189 char esdhc1_path[] = "/soc/esdhc@1580000";
190 bool sdhc2_en = false;
193 int ret, bus_num = 0;
195 #if defined(CONFIG_DM_I2C)
198 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
201 printf("%s: Cannot find udev for a bus %d\n", __func__,
205 ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
207 i2c_set_bus_num(bus_num);
208 /* IO1[7:3] is the field of board revision info. */
209 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
212 printf("Error reading i2c boot information!\n");
216 /* hwconfig method is used for RevD and later versions. */
217 if ((io & SW_REV_MASK) <= SW_REV_D) {
218 #ifdef CONFIG_HWCONFIG
219 if (hwconfig("esdhc1"))
224 * The I2C IO-expander for mux select is used to control
225 * the muxing of various onboard interfaces.
227 * IO0[3:2] indicates SDHC2 interface demultiplexer
230 * 01 - GPIO (to Arduino)
234 #if defined(CONFIG_DM_I2C)
235 ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
237 ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
240 printf("Error reading i2c boot information!\n");
244 mux_sdhc2 = (io & 0x0c) >> 2;
245 /* Enable SDHC2 only when use SDIO wifi and eMMC */
246 if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
250 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
253 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
254 sizeof("disabled"), 1);
259 int ft_board_setup(void *blob, bd_t *bd)
261 arch_fixup_fdt(blob);
263 ft_cpu_setup(blob, bd);
268 static int switch_to_bank1(void)
270 u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
271 int ret, bus_num = 0;
273 #if defined(CONFIG_DM_I2C)
276 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
279 printf("%s: Cannot find udev for a bus %d\n", __func__,
284 * --------------------------------------------------------------------
285 * |bus |I2C address| Device | Notes |
286 * --------------------------------------------------------------------
287 * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General |
288 * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output|
289 * | | | KW41GPIO) - NXP | (GPIO) expansion for the |
290 * | | | PCAL9555AHF | I2C bus |
291 * ----- --------------------------------------------------------------
292 * - mount three IO expander(PCAL9555AHF) on I2C1
294 * PCAL9555A device address
296 * --------------------------------------
297 * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
298 * --------------------------------------
299 * | fixed | hardware selectable|
301 * Output port 1(Pinter register bits = 0x03)
304 * P1_0 <---> CFG_MUX_QSPI_S0
305 * P1_1 <---> CFG_MUX_QSPI_S1
306 * CFG_MUX_QSPI_S[1:0] = 0b00
308 * QSPI chip-select demultiplexer select
309 * ---------------------------------------------------------------------
310 * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values
311 * ---------------------------------------------------------------------
312 * 0 | 0 |CS routed to SPI memory bank1(default)
313 * ---------------------------------------------------------------------
314 * 0 | 1 |CS routed to SPI memory bank2
315 * ---------------------------------------------------------------------
318 ret = dm_i2c_write(dev, offset_addr, &data, 1);
319 #else /* Non DM I2C support - will be removed */
320 i2c_set_bus_num(bus_num);
321 ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
325 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
326 chip_addr, offset_addr, data);
332 static int switch_to_bank2(void)
334 u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
336 int ret, i, bus_num = 0;
338 #if defined(CONFIG_DM_I2C)
341 ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
344 printf("%s: Cannot find udev for a bus %d\n", __func__,
348 #else /* Non DM I2C support - will be removed */
349 i2c_set_bus_num(bus_num);
353 * 1th step: config port 1
354 * - the port 1 pin is enabled as an output
355 * 2th step: output port 1
356 * - P1_[7:0] output 0xf5,
357 * then CFG_MUX_QSPI_S[1:0] equal to 0b01,
358 * CS routed to SPI memory bank2
360 for (i = 0; i < sizeof(data); i++) {
361 #if defined(CONFIG_DM_I2C)
362 ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
363 #else /* Non DM I2C support - will be removed */
364 ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
367 printf("i2c write error to chip : %u, addr : %u, data : %u\n",
368 chip_addr, offset_addr[i], data[i]);
377 static int convert_flash_bank(int bank)
382 case BOOT_FROM_UPPER_BANK:
383 ret = switch_to_bank2();
385 case BOOT_FROM_LOWER_BANK:
386 ret = switch_to_bank1();
396 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
400 return CMD_RET_USAGE;
401 if (strcmp(argv[1], "1") == 0)
402 convert_flash_bank(BOOT_FROM_LOWER_BANK);
403 else if (strcmp(argv[1], "2") == 0)
404 convert_flash_bank(BOOT_FROM_UPPER_BANK);
406 return CMD_RET_USAGE;
412 boot_bank, 2, 0, flash_bank_cmd,
413 "Flash bank Selection Control",
414 "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"