board/freescale/ls1012ardb/eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015-2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <net.h>
  10 #include <asm/io.h>
  11 #include <netdev.h>
  12 #include <fm_eth.h>
  13 #include <fsl_mdio.h>
  14 #include <malloc.h>
  15 #include <asm/types.h>
  16 #include <fsl_dtsec.h>
  17 #include <asm/arch/soc.h>
  18 #include <asm/arch-fsl-layerscape/config.h>
  19 #include <asm/arch-fsl-layerscape/immap_lsch2.h>
  20 #include <asm/arch/fsl_serdes.h>
  21 #include <net/pfe_eth/pfe_eth.h>
  22 #include <dm/platform_data/pfe_dm_eth.h>
  23 #include <i2c.h>
  24
  25 #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
  26
  27 static inline void ls1012ardb_reset_phy(void)
  28 {
  29 #ifdef CONFIG_TARGET_LS1012ARDB
  30         /* Through reset IO expander reset both RGMII and SGMII PHYs */
  31 #ifdef CONFIG_DM_I2C
  32         struct udevice *dev;
  33         int ret;
  34
  35         /*
  36          * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0).
  37          */
  38         ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR,
  39                                       1, &dev);
  40         if (ret) {
  41                 printf("%s: Cannot find udev for a bus %d\n", __func__,
  42                        0);
  43                 return;
  44         }
  45         /* Config port 0
  46          * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B
  47          *   are enabled as an output.
  48          */
  49         dm_i2c_reg_write(dev, 6, __PHY_MASK);
  50
  51         /*
  52          * Set port 0 output a value to reset ETH2 interface
  53          * - pin IOXP_RST_ETH2_B output 0b0
  54          */
  55         dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK);
  56         mdelay(10);
  57         dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK);
  58         /*
  59          * Set port 0 output a value to reset ETH1 interface
  60          * - pin IOXP_RST_ETH1_B output 0b0
  61          */
  62         mdelay(10);
  63         dm_i2c_reg_write(dev, 2, 0xFF);
  64 #else
  65         i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
  66         i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
  67         mdelay(10);
  68         i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
  69         mdelay(10);
  70         i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
  71 #endif
  72         mdelay(50);
  73 #endif
  74 }
  75
  76 int pfe_eth_board_init(struct udevice *dev)
  77 {
  78         static int init_done;
  79         struct mii_dev *bus;
  80         struct pfe_mdio_info mac_mdio_info;
  81         struct pfe_eth_dev *priv = dev_get_priv(dev);
  82         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  83
  84         int srds_s1 = in_be32(&gur->rcwsr[4]) &
  85                         FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  86         srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  87
  88         if (!init_done) {
  89                 ls1012ardb_reset_phy();
  90                 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
  91                 mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
  92
  93                 bus = pfe_mdio_init(&mac_mdio_info);
  94                 if (!bus) {
  95                         printf("Failed to register mdio\n");
  96                         return -1;
  97                 }
  98                 init_done = 1;
  99         }
 100
 101         pfe_set_mdio(priv->gemac_port,
 102                      miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
 103
 104         switch (srds_s1) {
 105         case 0x3508:
 106                 if (!priv->gemac_port) {
 107                         /* MAC1 */
 108                         pfe_set_phy_address_mode(priv->gemac_port,
 109                                                  CONFIG_PFE_EMAC1_PHY_ADDR,
 110                                                  PHY_INTERFACE_MODE_SGMII);
 111                 } else {
 112                         /* MAC2 */
 113                         pfe_set_phy_address_mode(priv->gemac_port,
 114                                                  CONFIG_PFE_EMAC2_PHY_ADDR,
 115                                                  PHY_INTERFACE_MODE_RGMII_TXID);
 116                 }
 117                 break;
 118         case 0x2208:
 119                 if (!priv->gemac_port) {
 120                         /* MAC1 */
 121                         pfe_set_phy_address_mode(priv->gemac_port,
 122                                                  CONFIG_PFE_EMAC1_PHY_ADDR,
 123                                                  PHY_INTERFACE_MODE_SGMII_2500);
 124                 } else {
 125                         /* MAC2 */
 126                         pfe_set_phy_address_mode(priv->gemac_port,
 127                                                  CONFIG_PFE_EMAC2_PHY_ADDR,
 128                                                  PHY_INTERFACE_MODE_SGMII_2500);
 129                 }
 130                 break;
 131         default:
 132                 printf("unsupported SerDes PRCTL= %d\n", srds_s1);
 133                 break;
 134         }
 135         return 0;
 136 }
 137
 138 static struct pfe_eth_pdata pfe_pdata0 = {
 139         .pfe_eth_pdata_mac = {
 140                 .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
 141                 .phy_interface = 0,
 142         },
 143
 144         .pfe_ddr_addr = {
 145                 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
 146                 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
 147         },
 148 };
 149
 150 static struct pfe_eth_pdata pfe_pdata1 = {
 151         .pfe_eth_pdata_mac = {
 152                 .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
 153                 .phy_interface = 1,
 154         },
 155
 156         .pfe_ddr_addr = {
 157                 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
 158                 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
 159         },
 160 };
 161
 162 U_BOOT_DEVICE(ls1012a_pfe0) = {
 163         .name = "pfe_eth",
 164         .platdata = &pfe_pdata0,
 165 };
 166
 167 U_BOOT_DEVICE(ls1012a_pfe1) = {
 168         .name = "pfe_eth",
 169         .platdata = &pfe_pdata1,
 170 };