board/freescale/imx8mq_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <hang.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/io.h>
  14 #include <errno.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/ddr.h>
  17 #include <asm/arch/imx8mq_pins.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/mach-imx/iomux-v3.h>
  21 #include <asm/mach-imx/gpio.h>
  22 #include <asm/mach-imx/mxc_i2c.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <mmc.h>
  25 #include <power/pmic.h>
  26 #include <power/pfuze100_pmic.h>
  27 #include <spl.h>
  28 #include "../common/pfuze.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 extern struct dram_timing_info dram_timing_b0;
  33
  34 static void spl_dram_init(void)
  35 {
  36         /* ddr init */
  37         if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
  38                 ddr_init(&dram_timing);
  39         else
  40                 ddr_init(&dram_timing_b0);
  41 }
  42
  43 #define I2C_PAD_CTRL    (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  44 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  45 static struct i2c_pads_info i2c_pad_info1 = {
  46         .scl = {
  47                 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
  48                 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  49                 .gp = IMX_GPIO_NR(5, 14),
  50         },
  51         .sda = {
  52                 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
  53                 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  54                 .gp = IMX_GPIO_NR(5, 15),
  55         },
  56 };
  57
  58 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 12)
  59 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
  60 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  61
  62 int board_mmc_getcd(struct mmc *mmc)
  63 {
  64         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  65         int ret = 0;
  66
  67         switch (cfg->esdhc_base) {
  68         case USDHC1_BASE_ADDR:
  69                 ret = 1;
  70                 break;
  71         case USDHC2_BASE_ADDR:
  72                 ret = !gpio_get_value(USDHC2_CD_GPIO);
  73                 return ret;
  74         }
  75
  76         return 1;
  77 }
  78
  79 #define USDHC_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
  80                          PAD_CTL_FSEL2)
  81 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
  82
  83 static iomux_v3_cfg_t const usdhc1_pads[] = {
  84         IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  95 };
  96
  97 static iomux_v3_cfg_t const usdhc2_pads[] = {
  98         IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  99         IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 100         IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 101         IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 102         IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
 103         IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 104         IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
 105         IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
 106 };
 107
 108 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 109         {USDHC1_BASE_ADDR, 0, 8},
 110         {USDHC2_BASE_ADDR, 0, 4},
 111 };
 112
 113 int board_mmc_init(bd_t *bis)
 114 {
 115         int i, ret;
 116         /*
 117          * According to the board_mmc_init() the following map is done:
 118          * (U-Boot device node)    (Physical Port)
 119          * mmc0                    USDHC1
 120          * mmc1                    USDHC2
 121          */
 122         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 123                 switch (i) {
 124                 case 0:
 125                         init_clk_usdhc(0);
 126                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
 127                         imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 128                                                          ARRAY_SIZE(usdhc1_pads));
 129                         gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
 130                         gpio_direction_output(USDHC1_PWR_GPIO, 0);
 131                         udelay(500);
 132                         gpio_direction_output(USDHC1_PWR_GPIO, 1);
 133                         break;
 134                 case 1:
 135                         init_clk_usdhc(1);
 136                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
 137                         imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
 138                                                          ARRAY_SIZE(usdhc2_pads));
 139                         gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
 140                         gpio_direction_output(USDHC2_PWR_GPIO, 0);
 141                         udelay(500);
 142                         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 143                         break;
 144                 default:
 145                         printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
 146                         return -EINVAL;
 147                 }
 148
 149                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 150                 if (ret)
 151                         return ret;
 152         }
 153
 154         return 0;
 155 }
 156
 157 #ifdef CONFIG_POWER
 158 #define I2C_PMIC        0
 159 int power_init_board(void)
 160 {
 161         struct pmic *p;
 162         int ret;
 163         unsigned int reg;
 164
 165         ret = power_pfuze100_init(I2C_PMIC);
 166         if (ret)
 167                 return -ENODEV;
 168
 169         p = pmic_get("PFUZE100");
 170         ret = pmic_probe(p);
 171         if (ret)
 172                 return -ENODEV;
 173
 174         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 175         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 176
 177         pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
 178         if ((reg & 0x3f) != 0x18) {
 179                 reg &= ~0x3f;
 180                 reg |= 0x18;
 181                 pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
 182         }
 183
 184         ret = pfuze_mode_init(p, APS_PFM);
 185         if (ret < 0)
 186                 return ret;
 187
 188         /* set SW3A standby mode to off */
 189         pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
 190         reg &= ~0xf;
 191         reg |= APS_OFF;
 192         pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
 193
 194         return 0;
 195 }
 196 #endif
 197
 198 void spl_board_init(void)
 199 {
 200         puts("Normal Boot\n");
 201 }
 202
 203 #ifdef CONFIG_SPL_LOAD_FIT
 204 int board_fit_config_name_match(const char *name)
 205 {
 206         /* Just empty function now - can't decide what to choose */
 207         debug("%s: %s\n", __func__, name);
 208
 209         return 0;
 210 }
 211 #endif
 212
 213 void board_init_f(ulong dummy)
 214 {
 215         int ret;
 216
 217         /* Clear global data */
 218         memset((void *)gd, 0, sizeof(gd_t));
 219
 220         arch_cpu_init();
 221
 222         init_uart_clk(0);
 223
 224         board_early_init_f();
 225
 226         timer_init();
 227
 228         preloader_console_init();
 229
 230         /* Clear the BSS. */
 231         memset(__bss_start, 0, __bss_end - __bss_start);
 232
 233         ret = spl_init();
 234         if (ret) {
 235                 debug("spl_init() failed: %d\n", ret);
 236                 hang();
 237         }
 238
 239         enable_tzc380();
 240
 241         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 242
 243         power_init_board();
 244
 245         /* DDR initialization */
 246         spl_dram_init();
 247
 248         board_init_r(NULL, 0);
 249 }