board/freescale/imx8mq_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <hang.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/io.h>
  14 #include <errno.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/ddr.h>
  17 #include <asm/arch/imx8mq_pins.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/mach-imx/iomux-v3.h>
  21 #include <asm/mach-imx/gpio.h>
  22 #include <asm/mach-imx/mxc_i2c.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <mmc.h>
  25 #include <linux/delay.h>
  26 #include <power/pmic.h>
  27 #include <power/pfuze100_pmic.h>
  28 #include <spl.h>
  29 #include "../common/pfuze.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 extern struct dram_timing_info dram_timing_b0;
  34
  35 static void spl_dram_init(void)
  36 {
  37         /* ddr init */
  38         if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
  39                 ddr_init(&dram_timing);
  40         else
  41                 ddr_init(&dram_timing_b0);
  42 }
  43
  44 #define I2C_PAD_CTRL    (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  45 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  46 static struct i2c_pads_info i2c_pad_info1 = {
  47         .scl = {
  48                 .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
  49                 .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  50                 .gp = IMX_GPIO_NR(5, 14),
  51         },
  52         .sda = {
  53                 .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
  54                 .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  55                 .gp = IMX_GPIO_NR(5, 15),
  56         },
  57 };
  58
  59 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 12)
  60 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
  61 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  62
  63 int board_mmc_getcd(struct mmc *mmc)
  64 {
  65         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  66         int ret = 0;
  67
  68         switch (cfg->esdhc_base) {
  69         case USDHC1_BASE_ADDR:
  70                 ret = 1;
  71                 break;
  72         case USDHC2_BASE_ADDR:
  73                 ret = !gpio_get_value(USDHC2_CD_GPIO);
  74                 return ret;
  75         }
  76
  77         return 1;
  78 }
  79
  80 #define USDHC_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
  81                          PAD_CTL_FSEL2)
  82 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
  83
  84 static iomux_v3_cfg_t const usdhc1_pads[] = {
  85         IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  96 };
  97
  98 static iomux_v3_cfg_t const usdhc2_pads[] = {
  99         IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 100         IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 101         IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 102         IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 103         IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
 104         IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
 105         IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
 106         IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
 107 };
 108
 109 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 110         {USDHC1_BASE_ADDR, 0, 8},
 111         {USDHC2_BASE_ADDR, 0, 4},
 112 };
 113
 114 int board_mmc_init(bd_t *bis)
 115 {
 116         int i, ret;
 117         /*
 118          * According to the board_mmc_init() the following map is done:
 119          * (U-Boot device node)    (Physical Port)
 120          * mmc0                    USDHC1
 121          * mmc1                    USDHC2
 122          */
 123         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 124                 switch (i) {
 125                 case 0:
 126                         init_clk_usdhc(0);
 127                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
 128                         imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 129                                                          ARRAY_SIZE(usdhc1_pads));
 130                         gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
 131                         gpio_direction_output(USDHC1_PWR_GPIO, 0);
 132                         udelay(500);
 133                         gpio_direction_output(USDHC1_PWR_GPIO, 1);
 134                         break;
 135                 case 1:
 136                         init_clk_usdhc(1);
 137                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
 138                         imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
 139                                                          ARRAY_SIZE(usdhc2_pads));
 140                         gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
 141                         gpio_direction_output(USDHC2_PWR_GPIO, 0);
 142                         udelay(500);
 143                         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 144                         break;
 145                 default:
 146                         printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
 147                         return -EINVAL;
 148                 }
 149
 150                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 151                 if (ret)
 152                         return ret;
 153         }
 154
 155         return 0;
 156 }
 157
 158 #ifdef CONFIG_POWER
 159 #define I2C_PMIC        0
 160 int power_init_board(void)
 161 {
 162         struct pmic *p;
 163         int ret;
 164         unsigned int reg;
 165
 166         ret = power_pfuze100_init(I2C_PMIC);
 167         if (ret)
 168                 return -ENODEV;
 169
 170         p = pmic_get("PFUZE100");
 171         ret = pmic_probe(p);
 172         if (ret)
 173                 return -ENODEV;
 174
 175         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 176         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 177
 178         pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
 179         if ((reg & 0x3f) != 0x18) {
 180                 reg &= ~0x3f;
 181                 reg |= 0x18;
 182                 pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
 183         }
 184
 185         ret = pfuze_mode_init(p, APS_PFM);
 186         if (ret < 0)
 187                 return ret;
 188
 189         /* set SW3A standby mode to off */
 190         pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
 191         reg &= ~0xf;
 192         reg |= APS_OFF;
 193         pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
 194
 195         return 0;
 196 }
 197 #endif
 198
 199 void spl_board_init(void)
 200 {
 201         puts("Normal Boot\n");
 202 }
 203
 204 #ifdef CONFIG_SPL_LOAD_FIT
 205 int board_fit_config_name_match(const char *name)
 206 {
 207         /* Just empty function now - can't decide what to choose */
 208         debug("%s: %s\n", __func__, name);
 209
 210         return 0;
 211 }
 212 #endif
 213
 214 void board_init_f(ulong dummy)
 215 {
 216         int ret;
 217
 218         /* Clear global data */
 219         memset((void *)gd, 0, sizeof(gd_t));
 220
 221         arch_cpu_init();
 222
 223         init_uart_clk(0);
 224
 225         board_early_init_f();
 226
 227         timer_init();
 228
 229         preloader_console_init();
 230
 231         /* Clear the BSS. */
 232         memset(__bss_start, 0, __bss_end - __bss_start);
 233
 234         ret = spl_init();
 235         if (ret) {
 236                 debug("spl_init() failed: %d\n", ret);
 237                 hang();
 238         }
 239
 240         enable_tzc380();
 241
 242         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 243
 244         power_init_board();
 245
 246         /* DDR initialization */
 247         spl_dram_init();
 248
 249         board_init_r(NULL, 0);
 250 }