board/freescale/imx8mp_evk/spl.c

   1 /*
   2  * Copyright 2018-2019 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <hang.h>
  11 #include <image.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <spl.h>
  15 #include <asm/io.h>
  16 #include <errno.h>
  17 #include <asm/io.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/arch/imx8mp_pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <power/pmic.h>
  23
  24 #include <power/pca9450.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/mach-imx/gpio.h>
  27 #include <asm/mach-imx/mxc_i2c.h>
  28 #include <fsl_esdhc.h>
  29 #include <mmc.h>
  30 #include <asm/arch/ddr.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 int spl_board_boot_device(enum boot_device boot_dev_spl)
  35 {
  36         return BOOT_DEVICE_BOOTROM;
  37 }
  38
  39 void spl_dram_init(void)
  40 {
  41         ddr_init(&dram_timing);
  42 }
  43
  44 void spl_board_init(void)
  45 {
  46         puts("Normal Boot\n");
  47 }
  48
  49 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  50 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  51 struct i2c_pads_info i2c_pad_info1 = {
  52         .scl = {
  53                 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
  54                 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  55                 .gp = IMX_GPIO_NR(5, 14),
  56         },
  57         .sda = {
  58                 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
  59                 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  60                 .gp = IMX_GPIO_NR(5, 15),
  61         },
  62 };
  63
  64 #ifdef CONFIG_POWER
  65 #define I2C_PMIC        0
  66 int power_init_board(void)
  67 {
  68         struct pmic *p;
  69         int ret;
  70
  71         ret = power_pca9450b_init(I2C_PMIC);
  72         if (ret)
  73                 printf("power init failed");
  74         p = pmic_get("PCA9450");
  75         pmic_probe(p);
  76
  77         /* BUCKxOUT_DVS0/1 control BUCK123 output */
  78         pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
  79
  80         /*
  81          * increase VDD_SOC to typical value 0.95V before first
  82          * DRAM access, set DVS1 to 0.85v for suspend.
  83          * Enable DVS control through PMIC_STBY_REQ and
  84          * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
  85          */
  86         pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
  87         pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
  88         pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
  89
  90         /* set WDOG_B_CFG to cold reset */
  91         pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
  92
  93         return 0;
  94 }
  95 #endif
  96
  97 #ifdef CONFIG_SPL_LOAD_FIT
  98 int board_fit_config_name_match(const char *name)
  99 {
 100         /* Just empty function now - can't decide what to choose */
 101         debug("%s: %s\n", __func__, name);
 102
 103         return 0;
 104 }
 105 #endif
 106
 107 void board_init_f(ulong dummy)
 108 {
 109         int ret;
 110
 111         arch_cpu_init();
 112
 113         init_uart_clk(1);
 114
 115         board_early_init_f();
 116
 117         preloader_console_init();
 118
 119         /* Clear the BSS. */
 120         memset(__bss_start, 0, __bss_end - __bss_start);
 121
 122         ret = spl_init();
 123         if (ret) {
 124                 debug("spl_init() failed: %d\n", ret);
 125                 hang();
 126         }
 127
 128         enable_tzc380();
 129
 130         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 131
 132         power_init_board();
 133
 134         /* DDR initialization */
 135         spl_dram_init();
 136
 137         board_init_r(NULL, 0);
 138 }