1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/mach-imx/iomux-v3.h>
9 #include <asm-generic/gpio.h>
10 #include <asm/arch/imx8mp_pins.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/mach-imx/gpio.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
17 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
19 static iomux_v3_cfg_t const uart_pads[] = {
20 MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
21 MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
24 static iomux_v3_cfg_t const wdog_pads[] = {
25 MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
28 int board_early_init_f(void)
30 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
32 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
36 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
43 /* rom_pointer[1] contains the size of TEE occupies */
45 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
47 gd->ram_size = PHYS_SDRAM_SIZE;
49 #if CONFIG_NR_DRAM_BANKS > 1
50 gd->ram_size += PHYS_SDRAM_2_SIZE;
56 int dram_init_banksize(void)
58 gd->bd->bi_dram[0].start = PHYS_SDRAM;
61 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE - rom_pointer[1];
63 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
65 #if CONFIG_NR_DRAM_BANKS > 1
66 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
67 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
73 phys_size_t get_effective_memsize(void)
76 return (PHYS_SDRAM_SIZE - rom_pointer[1]);
78 return PHYS_SDRAM_SIZE;
86 int board_late_init(void)
88 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
89 env_set("board_name", "EVK");
90 env_set("board_rev", "iMX8MP");