1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/mach-imx/iomux-v3.h>
11 #include <asm-generic/gpio.h>
12 #include <asm/arch/imx8mp_pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/gpio.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
19 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
21 static iomux_v3_cfg_t const uart_pads[] = {
22 MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
23 MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
26 static iomux_v3_cfg_t const wdog_pads[] = {
27 MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
30 int board_early_init_f(void)
32 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
34 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
38 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
45 /* rom_pointer[1] contains the size of TEE occupies */
47 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
49 gd->ram_size = PHYS_SDRAM_SIZE;
51 #if CONFIG_NR_DRAM_BANKS > 1
52 gd->ram_size += PHYS_SDRAM_2_SIZE;
58 int dram_init_banksize(void)
60 gd->bd->bi_dram[0].start = PHYS_SDRAM;
63 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE - rom_pointer[1];
65 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
67 #if CONFIG_NR_DRAM_BANKS > 1
68 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
69 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
75 phys_size_t get_effective_memsize(void)
78 return (PHYS_SDRAM_SIZE - rom_pointer[1]);
80 return PHYS_SDRAM_SIZE;
88 int board_late_init(void)
90 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
91 env_set("board_name", "EVK");
92 env_set("board_rev", "iMX8MP");