board/freescale/imx8mn_evk/spl.c

   1 /*
   2  * Copyright 2018-2019 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <hang.h>
  11 #include <image.h>
  12 #include <init.h>
  13 #include <spl.h>
  14 #include <asm/io.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/imx8mn_pins.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/arch/ddr.h>
  21
  22 #include <dm/uclass.h>
  23 #include <dm/device.h>
  24 #include <dm/uclass-internal.h>
  25 #include <dm/device-internal.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int spl_board_boot_device(enum boot_device boot_dev_spl)
  30 {
  31         return BOOT_DEVICE_BOOTROM;
  32 }
  33
  34 void spl_dram_init(void)
  35 {
  36         ddr_init(&dram_timing);
  37 }
  38
  39 void spl_board_init(void)
  40 {
  41         struct udevice *dev;
  42         int ret;
  43
  44         puts("Normal Boot\n");
  45
  46         ret = uclass_get_device_by_name(UCLASS_CLK,
  47                                         "clock-controller@30380000",
  48                                         &dev);
  49         if (ret < 0)
  50                 printf("Failed to find clock node. Check device tree\n");
  51 }
  52
  53 #ifdef CONFIG_SPL_LOAD_FIT
  54 int board_fit_config_name_match(const char *name)
  55 {
  56         /* Just empty function now - can't decide what to choose */
  57         debug("%s: %s\n", __func__, name);
  58
  59         return 0;
  60 }
  61 #endif
  62
  63 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  64 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  65
  66 static iomux_v3_cfg_t const uart_pads[] = {
  67         IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  68         IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  69 };
  70
  71 static iomux_v3_cfg_t const wdog_pads[] = {
  72         IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  73 };
  74
  75 int board_early_init_f(void)
  76 {
  77         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  78
  79         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  80
  81         set_wdog_reset(wdog);
  82
  83         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  84
  85         init_uart_clk(1);
  86
  87         return 0;
  88 }
  89
  90 void board_init_f(ulong dummy)
  91 {
  92         int ret;
  93
  94         arch_cpu_init();
  95
  96         init_uart_clk(1);
  97
  98         board_early_init_f();
  99
 100         timer_init();
 101
 102         preloader_console_init();
 103
 104         /* Clear the BSS. */
 105         memset(__bss_start, 0, __bss_end - __bss_start);
 106
 107         ret = spl_init();
 108         if (ret) {
 109                 debug("spl_init() failed: %d\n", ret);
 110                 hang();
 111         }
 112
 113         enable_tzc380();
 114
 115         /* DDR initialization */
 116         spl_dram_init();
 117
 118         board_init_r(NULL, 0);
 119 }