board/freescale/imx8mn_evk/spl.c

   1 /*
   2  * Copyright 2018-2019 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <hang.h>
  10 #include <spl.h>
  11 #include <asm/io.h>
  12 #include <asm/mach-imx/iomux-v3.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx8mn_pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/arch/ddr.h>
  18
  19 #include <dm/uclass.h>
  20 #include <dm/device.h>
  21 #include <dm/uclass-internal.h>
  22 #include <dm/device-internal.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 int spl_board_boot_device(enum boot_device boot_dev_spl)
  27 {
  28         return BOOT_DEVICE_BOOTROM;
  29 }
  30
  31 void spl_dram_init(void)
  32 {
  33         ddr_init(&dram_timing);
  34 }
  35
  36 void spl_board_init(void)
  37 {
  38         struct udevice *dev;
  39         int ret;
  40
  41         puts("Normal Boot\n");
  42
  43         ret = uclass_get_device_by_name(UCLASS_CLK,
  44                                         "clock-controller@30380000",
  45                                         &dev);
  46         if (ret < 0)
  47                 printf("Failed to find clock node. Check device tree\n");
  48 }
  49
  50 #ifdef CONFIG_SPL_LOAD_FIT
  51 int board_fit_config_name_match(const char *name)
  52 {
  53         /* Just empty function now - can't decide what to choose */
  54         debug("%s: %s\n", __func__, name);
  55
  56         return 0;
  57 }
  58 #endif
  59
  60 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  61 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  62
  63 static iomux_v3_cfg_t const uart_pads[] = {
  64         IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  65         IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  66 };
  67
  68 static iomux_v3_cfg_t const wdog_pads[] = {
  69         IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  70 };
  71
  72 int board_early_init_f(void)
  73 {
  74         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  75
  76         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  77
  78         set_wdog_reset(wdog);
  79
  80         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  81
  82         init_uart_clk(1);
  83
  84         return 0;
  85 }
  86
  87 void board_init_f(ulong dummy)
  88 {
  89         int ret;
  90
  91         arch_cpu_init();
  92
  93         init_uart_clk(1);
  94
  95         board_early_init_f();
  96
  97         timer_init();
  98
  99         preloader_console_init();
 100
 101         /* Clear the BSS. */
 102         memset(__bss_start, 0, __bss_end - __bss_start);
 103
 104         ret = spl_init();
 105         if (ret) {
 106                 debug("spl_init() failed: %d\n", ret);
 107                 hang();
 108         }
 109
 110         enable_tzc380();
 111
 112         /* DDR initialization */
 113         spl_dram_init();
 114
 115         board_init_r(NULL, 0);
 116 }