board/freescale/imx8mm_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <spl.h>
   8 #include <asm/io.h>
   9 #include <asm/mach-imx/iomux-v3.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx8mm_pins.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/mach-imx/boot_mode.h>
  14 #include <asm/arch/ddr.h>
  15
  16 #include <dm/uclass.h>
  17 #include <dm/device.h>
  18 #include <dm/uclass-internal.h>
  19 #include <dm/device-internal.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 int spl_board_boot_device(enum boot_device boot_dev_spl)
  24 {
  25         switch (boot_dev_spl) {
  26         case SD2_BOOT:
  27         case MMC2_BOOT:
  28                 return BOOT_DEVICE_MMC1;
  29         case SD3_BOOT:
  30         case MMC3_BOOT:
  31                 return BOOT_DEVICE_MMC2;
  32         default:
  33                 return BOOT_DEVICE_NONE;
  34         }
  35 }
  36
  37 void spl_dram_init(void)
  38 {
  39         ddr_init(&dram_timing);
  40 }
  41
  42 void spl_board_init(void)
  43 {
  44         puts("Normal Boot\n");
  45 }
  46
  47 #ifdef CONFIG_SPL_LOAD_FIT
  48 int board_fit_config_name_match(const char *name)
  49 {
  50         /* Just empty function now - can't decide what to choose */
  51         debug("%s: %s\n", __func__, name);
  52
  53         return 0;
  54 }
  55 #endif
  56
  57 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  58 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  59
  60 static iomux_v3_cfg_t const uart_pads[] = {
  61         IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  62         IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63 };
  64
  65 static iomux_v3_cfg_t const wdog_pads[] = {
  66         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  67 };
  68
  69 int board_early_init_f(void)
  70 {
  71         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  72
  73         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  74
  75         set_wdog_reset(wdog);
  76
  77         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  78
  79         return 0;
  80 }
  81
  82 void board_init_f(ulong dummy)
  83 {
  84         struct udevice *dev;
  85         int ret;
  86
  87         arch_cpu_init();
  88
  89         init_uart_clk(1);
  90
  91         board_early_init_f();
  92
  93         timer_init();
  94
  95         preloader_console_init();
  96
  97         /* Clear the BSS. */
  98         memset(__bss_start, 0, __bss_end - __bss_start);
  99
 100         ret = spl_early_init();
 101         if (ret) {
 102                 debug("spl_early_init() failed: %d\n", ret);
 103                 hang();
 104         }
 105
 106         ret = uclass_get_device_by_name(UCLASS_CLK,
 107                                         "clock-controller@30380000",
 108                                         &dev);
 109         if (ret < 0) {
 110                 printf("Failed to find clock node. Check device tree\n");
 111                 hang();
 112         }
 113
 114         enable_tzc380();
 115
 116         /* DDR initialization */
 117         spl_dram_init();
 118
 119         board_init_r(NULL, 0);
 120 }
 121
 122 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 123 {
 124         puts ("resetting ...\n");
 125
 126         reset_cpu(WDOG1_BASE_ADDR);
 127
 128         return 0;
 129 }