board/freescale/imx8mm_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <cpu_func.h>
   9 #include <hang.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <spl.h>
  13 #include <asm/io.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/imx8mm_pins.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/mach-imx/boot_mode.h>
  19 #include <asm/arch/ddr.h>
  20
  21 #include <dm/uclass.h>
  22 #include <dm/device.h>
  23 #include <dm/uclass-internal.h>
  24 #include <dm/device-internal.h>
  25
  26 #include <power/pmic.h>
  27 #include <power/bd71837.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int spl_board_boot_device(enum boot_device boot_dev_spl)
  32 {
  33         switch (boot_dev_spl) {
  34         case SD2_BOOT:
  35         case MMC2_BOOT:
  36                 return BOOT_DEVICE_MMC1;
  37         case SD3_BOOT:
  38         case MMC3_BOOT:
  39                 return BOOT_DEVICE_MMC2;
  40         default:
  41                 return BOOT_DEVICE_NONE;
  42         }
  43 }
  44
  45 static void spl_dram_init(void)
  46 {
  47         ddr_init(&dram_timing);
  48 }
  49
  50 void spl_board_init(void)
  51 {
  52         puts("Normal Boot\n");
  53 }
  54
  55 #ifdef CONFIG_SPL_LOAD_FIT
  56 int board_fit_config_name_match(const char *name)
  57 {
  58         /* Just empty function now - can't decide what to choose */
  59         debug("%s: %s\n", __func__, name);
  60
  61         return 0;
  62 }
  63 #endif
  64
  65 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  66 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  67
  68 static iomux_v3_cfg_t const uart_pads[] = {
  69         IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  70         IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  71 };
  72
  73 static iomux_v3_cfg_t const wdog_pads[] = {
  74         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  75 };
  76
  77 int board_early_init_f(void)
  78 {
  79         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  80
  81         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  82
  83         set_wdog_reset(wdog);
  84
  85         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  86
  87         return 0;
  88 }
  89
  90 static int power_init_board(void)
  91 {
  92         struct udevice *dev;
  93         int ret;
  94
  95         ret = pmic_get("pmic@4b", &dev);
  96         if (ret == -ENODEV) {
  97                 puts("No pmic\n");
  98                 return 0;
  99         }
 100         if (ret != 0)
 101                 return ret;
 102
 103         /* decrease RESET key long push time from the default 10s to 10ms */
 104         pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
 105
 106         /* unlock the PMIC regs */
 107         pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
 108
 109         /* increase VDD_SOC to typical value 0.85v before first DRAM access */
 110         pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 111
 112         /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
 113         pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 114
 115 #ifndef CONFIG_IMX8M_LPDDR4
 116         /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
 117         pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
 118 #endif
 119
 120         /* lock the PMIC regs */
 121         pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
 122
 123         return 0;
 124 }
 125
 126 void board_init_f(ulong dummy)
 127 {
 128         struct udevice *dev;
 129         int ret;
 130
 131         arch_cpu_init();
 132
 133         init_uart_clk(1);
 134
 135         board_early_init_f();
 136
 137         timer_init();
 138
 139         preloader_console_init();
 140
 141         /* Clear the BSS. */
 142         memset(__bss_start, 0, __bss_end - __bss_start);
 143
 144         ret = spl_early_init();
 145         if (ret) {
 146                 debug("spl_early_init() failed: %d\n", ret);
 147                 hang();
 148         }
 149
 150         ret = uclass_get_device_by_name(UCLASS_CLK,
 151                                         "clock-controller@30380000",
 152                                         &dev);
 153         if (ret < 0) {
 154                 printf("Failed to find clock node. Check device tree\n");
 155                 hang();
 156         }
 157
 158         enable_tzc380();
 159
 160         power_init_board();
 161
 162         /* DDR initialization */
 163         spl_dram_init();
 164
 165         board_init_r(NULL, 0);
 166 }