board/freescale/b4860qds/b4860qds.c

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/errno.h>
  15 #include <asm/cache.h>
  16 #include <asm/immap_85xx.h>
  17 #include <asm/fsl_law.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <asm/fsl_portals.h>
  20 #include <asm/fsl_liodn.h>
  21 #include <fm_eth.h>
  22
  23 #include "../common/qixis.h"
  24 #include "../common/vsc3316_3308.h"
  25 #include "../common/idt8t49n222a_serdes_clk.h"
  26 #include "../common/zm7300.h"
  27 #include "b4860qds.h"
  28 #include "b4860qds_qixis.h"
  29 #include "b4860qds_crossbar_con.h"
  30
  31 #define CLK_MUX_SEL_MASK        0x4
  32 #define ETH_PHY_CLK_OUT         0x4
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 int checkboard(void)
  37 {
  38         char buf[64];
  39         u8 sw;
  40         struct cpu_type *cpu = gd->arch.cpu;
  41         static const char *const freq[] = {"100", "125", "156.25", "161.13",
  42                                                 "122.88", "122.88", "122.88"};
  43         int clock;
  44
  45         printf("Board: %sQDS, ", cpu->name);
  46         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  47                 QIXIS_READ(id), QIXIS_READ(arch));
  48
  49         sw = QIXIS_READ(brdcfg[0]);
  50         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  51
  52         if (sw < 0x8)
  53                 printf("vBank: %d\n", sw);
  54         else if (sw >= 0x8 && sw <= 0xE)
  55                 puts("NAND\n");
  56         else
  57                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  58
  59         printf("FPGA: v%d (%s), build %d",
  60                 (int)QIXIS_READ(scver), qixis_read_tag(buf),
  61                 (int)qixis_read_minor());
  62         /* the timestamp string contains "\n" at the end */
  63         printf(" on %s", qixis_read_time(buf));
  64
  65         /*
  66          * Display the actual SERDES reference clocks as configured by the
  67          * dip switches on the board.  Note that the SWx registers could
  68          * technically be set to force the reference clocks to match the
  69          * values that the SERDES expects (or vice versa).  For now, however,
  70          * we just display both values and hope the user notices when they
  71          * don't match.
  72          */
  73         puts("SERDES Reference Clocks: ");
  74         sw = QIXIS_READ(brdcfg[2]);
  75         clock = (sw >> 5) & 7;
  76         printf("Bank1=%sMHz ", freq[clock]);
  77         sw = QIXIS_READ(brdcfg[4]);
  78         clock = (sw >> 6) & 3;
  79         printf("Bank2=%sMHz\n", freq[clock]);
  80
  81         return 0;
  82 }
  83
  84 int select_i2c_ch_pca(u8 ch)
  85 {
  86         int ret;
  87
  88         /* Selecting proper channel via PCA*/
  89         ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
  90         if (ret) {
  91                 printf("PCA: failed to select proper channel.\n");
  92                 return ret;
  93         }
  94
  95         return 0;
  96 }
  97
  98 /*
  99  * read_voltage from sensor on I2C bus
 100  * We use average of 4 readings, waiting for 532us befor another reading
 101  */
 102 #define WAIT_FOR_ADC    532     /* wait for 532 microseconds for ADC */
 103 #define NUM_READINGS    4       /* prefer to be power of 2 for efficiency */
 104
 105 static inline int read_voltage(void)
 106 {
 107         int i, ret, voltage_read = 0;
 108         u16 vol_mon;
 109
 110         for (i = 0; i < NUM_READINGS; i++) {
 111                 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
 112                         I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
 113                 if (ret) {
 114                         printf("VID: failed to read core voltage\n");
 115                         return ret;
 116                 }
 117                 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
 118                         printf("VID: Core voltage sensor error\n");
 119                         return -1;
 120                 }
 121                 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
 122                 /* LSB = 4mv */
 123                 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
 124                 udelay(WAIT_FOR_ADC);
 125         }
 126         /* calculate the average */
 127         voltage_read /= NUM_READINGS;
 128
 129         return voltage_read;
 130 }
 131
 132 static int adjust_vdd(ulong vdd_override)
 133 {
 134         int re_enable = disable_interrupts();
 135         ccsr_gur_t __iomem *gur =
 136                 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 137         u32 fusesr;
 138         u8 vid;
 139         int vdd_target, vdd_last;
 140         int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
 141         int ret;
 142         unsigned int orig_i2c_speed;
 143         unsigned long vdd_string_override;
 144         char *vdd_string;
 145         static const uint16_t vdd[32] = {
 146                 0,      /* unused */
 147                 9875,   /* 0.9875V */
 148                 9750,
 149                 9625,
 150                 9500,
 151                 9375,
 152                 9250,
 153                 9125,
 154                 9000,
 155                 8875,
 156                 8750,
 157                 8625,
 158                 8500,
 159                 8375,
 160                 8250,
 161                 8125,
 162                 10000,  /* 1.0000V */
 163                 10125,
 164                 10250,
 165                 10375,
 166                 10500,
 167                 10625,
 168                 10750,
 169                 10875,
 170                 11000,
 171                 0,      /* reserved */
 172         };
 173         struct vdd_drive {
 174                 u8 vid;
 175                 unsigned voltage;
 176         };
 177
 178         ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
 179         if (ret) {
 180                 printf("VID: I2c failed to switch channel\n");
 181                 ret = -1;
 182                 goto exit;
 183         }
 184
 185         /* get the voltage ID from fuse status register */
 186         fusesr = in_be32(&gur->dcfg_fusesr);
 187         vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
 188                 FSL_CORENET_DCFG_FUSESR_VID_MASK;
 189         if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
 190                 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
 191                         FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
 192         }
 193         vdd_target = vdd[vid];
 194         debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
 195               vid, vdd_target/10);
 196
 197         /* check override variable for overriding VDD */
 198         vdd_string = getenv("b4qds_vdd_mv");
 199         if (vdd_override == 0 && vdd_string &&
 200             !strict_strtoul(vdd_string, 10, &vdd_string_override))
 201                 vdd_override = vdd_string_override;
 202         if (vdd_override >= 819 && vdd_override <= 1212) {
 203                 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
 204                 debug("VDD override is %lu\n", vdd_override);
 205         } else if (vdd_override != 0) {
 206                 printf("Invalid value.\n");
 207         }
 208
 209         if (vdd_target == 0) {
 210                 printf("VID: VID not used\n");
 211                 ret = 0;
 212                 goto exit;
 213         }
 214
 215         /*
 216          * Read voltage monitor to check real voltage.
 217          * Voltage monitor LSB is 4mv.
 218          */
 219         vdd_last = read_voltage();
 220         if (vdd_last < 0) {
 221                 printf("VID: abort VID adjustment\n");
 222                 ret = -1;
 223                 goto exit;
 224         }
 225
 226         debug("VID: Core voltage is at %d mV\n", vdd_last);
 227         ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
 228         if (ret) {
 229                 printf("VID: I2c failed to switch channel to DPM\n");
 230                 ret = -1;
 231                 goto exit;
 232         }
 233
 234         /* Round up to the value of step of Voltage regulator */
 235         voltage = roundup(vdd_target, ZM_STEP);
 236         debug("VID: rounded up voltage = %d\n", voltage);
 237
 238         /* lower the speed to 100kHz to access ZM7300 device */
 239         debug("VID: Setting bus speed to 100KHz if not already set\n");
 240         orig_i2c_speed = i2c_get_bus_speed();
 241         if (orig_i2c_speed != 100000)
 242                 i2c_set_bus_speed(100000);
 243
 244         /* Read the existing level on board, if equal to requsted one,
 245            no need to re-set */
 246         existing_voltage = zm_read_voltage();
 247
 248         /* allowing the voltage difference of one step 0.0125V acceptable */
 249         if ((existing_voltage >= voltage) &&
 250             (existing_voltage < (voltage + ZM_STEP))) {
 251                 debug("VID: voltage already set as requested,returning\n");
 252                 ret = existing_voltage;
 253                 goto out;
 254         }
 255         debug("VID: Changing voltage for board from %dmV to %dmV\n",
 256               existing_voltage/10, voltage/10);
 257
 258         if (zm_disable_wp() < 0) {
 259                 ret = -1;
 260                 goto out;
 261         }
 262         /* Change Voltage: the change is done through all the steps in the
 263            way, to avoid reset to the board due to power good signal fail
 264            in big voltage change gap jump.
 265         */
 266         if (existing_voltage > voltage) {
 267                 temp_voltage = existing_voltage - ZM_STEP;
 268                         while (temp_voltage >= voltage) {
 269                                 ret = zm_write_voltage(temp_voltage);
 270                                 if (ret == temp_voltage) {
 271                                         temp_voltage -= ZM_STEP;
 272                                 } else {
 273                                         /* ZM7300 device failed to set
 274                                          * the voltage */
 275                                         printf
 276                                         ("VID:Stepping down vol failed:%dmV\n",
 277                                          temp_voltage/10);
 278                                      ret = -1;
 279                                      goto out;
 280                                 }
 281                         }
 282         } else {
 283                 temp_voltage = existing_voltage + ZM_STEP;
 284                         while (temp_voltage < (voltage + ZM_STEP)) {
 285                                 ret = zm_write_voltage(temp_voltage);
 286                                 if (ret == temp_voltage) {
 287                                         temp_voltage += ZM_STEP;
 288                                 } else {
 289                                         /* ZM7300 device failed to set
 290                                          * the voltage */
 291                                         printf
 292                                         ("VID:Stepping up vol failed:%dmV\n",
 293                                          temp_voltage/10);
 294                                      ret = -1;
 295                                      goto out;
 296                                 }
 297                         }
 298         }
 299
 300         if (zm_enable_wp() < 0)
 301                 ret = -1;
 302
 303         /* restore the speed to 400kHz */
 304 out:    debug("VID: Restore the I2C bus speed to %dKHz\n",
 305                                 orig_i2c_speed/1000);
 306         i2c_set_bus_speed(orig_i2c_speed);
 307         if (ret < 0)
 308                 goto exit;
 309
 310         ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
 311         if (ret) {
 312                 printf("VID: I2c failed to switch channel\n");
 313                 ret = -1;
 314                 goto exit;
 315         }
 316         vdd_last = read_voltage();
 317         select_i2c_ch_pca(I2C_CH_DEFAULT);
 318
 319         if (vdd_last > 0)
 320                 printf("VID: Core voltage %d mV\n", vdd_last);
 321         else
 322                 ret = -1;
 323
 324 exit:
 325         if (re_enable)
 326                 enable_interrupts();
 327         return ret;
 328 }
 329
 330 int configure_vsc3316_3308(void)
 331 {
 332         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 333         unsigned int num_vsc16_con, num_vsc08_con;
 334         u32 serdes1_prtcl, serdes2_prtcl;
 335         int ret;
 336
 337         serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
 338                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 339         if (!serdes1_prtcl) {
 340                 printf("SERDES1 is not enabled\n");
 341                 return 0;
 342         }
 343         serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 344         debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
 345
 346         serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
 347                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 348         if (!serdes2_prtcl) {
 349                 printf("SERDES2 is not enabled\n");
 350                 return 0;
 351         }
 352         serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 353         debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
 354
 355         switch (serdes1_prtcl) {
 356         case 0x29:
 357         case 0x2a:
 358         case 0x2C:
 359         case 0x2D:
 360         case 0x2E:
 361                         /*
 362                          * Configuration:
 363                          * SERDES: 1
 364                          * Lanes: A,B: SGMII
 365                          * Lanes: C,D,E,F,G,H: CPRI
 366                          */
 367                 debug("Configuring crossbar to use onboard SGMII PHYs:"
 368                                 "srds_prctl:%x\n", serdes1_prtcl);
 369                 num_vsc16_con = NUM_CON_VSC3316;
 370                 /* Configure VSC3316 crossbar switch */
 371                 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 372                 if (!ret) {
 373                         ret = vsc3316_config(VSC3316_TX_ADDRESS,
 374                                         vsc16_tx_4sfp_sgmii_12_56,
 375                                         num_vsc16_con);
 376                         if (ret)
 377                                 return ret;
 378                         ret = vsc3316_config(VSC3316_RX_ADDRESS,
 379                                         vsc16_rx_4sfp_sgmii_12_56,
 380                                         num_vsc16_con);
 381                         if (ret)
 382                                 return ret;
 383                 } else {
 384                         return ret;
 385                 }
 386                 break;
 387
 388         case 0x01:
 389         case 0x02:
 390         case 0x04:
 391         case 0x05:
 392         case 0x06:
 393         case 0x07:
 394         case 0x08:
 395         case 0x09:
 396         case 0x0A:
 397         case 0x0B:
 398         case 0x0C:
 399         case 0x2F:
 400         case 0x30:
 401         case 0x32:
 402         case 0x33:
 403         case 0x34:
 404         case 0x39:
 405         case 0x3A:
 406         case 0x3C:
 407         case 0x3D:
 408         case 0x5C:
 409         case 0x5D:
 410                         /*
 411                          * Configuration:
 412                          * SERDES: 1
 413                          * Lanes: A,B: AURORA
 414                          * Lanes: C,d: SGMII
 415                          * Lanes: E,F,G,H: CPRI
 416                          */
 417                 debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
 418                                 " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
 419                 num_vsc16_con = NUM_CON_VSC3316;
 420                 /* Configure VSC3316 crossbar switch */
 421                 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 422                 if (!ret) {
 423                         ret = vsc3316_config(VSC3316_TX_ADDRESS,
 424                                         vsc16_tx_sfp_sgmii_aurora,
 425                                         num_vsc16_con);
 426                         if (ret)
 427                                 return ret;
 428                         ret = vsc3316_config(VSC3316_RX_ADDRESS,
 429                                         vsc16_rx_sfp_sgmii_aurora,
 430                                         num_vsc16_con);
 431                         if (ret)
 432                                 return ret;
 433                 } else {
 434                         return ret;
 435                 }
 436                 break;
 437
 438 #ifdef CONFIG_PPC_B4420
 439         case 0x17:
 440         case 0x18:
 441                         /*
 442                          * Configuration:
 443                          * SERDES: 1
 444                          * Lanes: A,B,C,D: SGMII
 445                          * Lanes: E,F,G,H: CPRI
 446                          */
 447                 debug("Configuring crossbar to use onboard SGMII PHYs:"
 448                                 "srds_prctl:%x\n", serdes1_prtcl);
 449                 num_vsc16_con = NUM_CON_VSC3316;
 450                 /* Configure VSC3316 crossbar switch */
 451                 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 452                 if (!ret) {
 453                         ret = vsc3316_config(VSC3316_TX_ADDRESS,
 454                                         vsc16_tx_sgmii_lane_cd, num_vsc16_con);
 455                         if (ret)
 456                                 return ret;
 457                         ret = vsc3316_config(VSC3316_RX_ADDRESS,
 458                                         vsc16_rx_sgmii_lane_cd, num_vsc16_con);
 459                         if (ret)
 460                                 return ret;
 461                 } else {
 462                         return ret;
 463                 }
 464                 break;
 465 #endif
 466
 467         case 0x3E:
 468         case 0x0D:
 469         case 0x0E:
 470         case 0x12:
 471                 num_vsc16_con = NUM_CON_VSC3316;
 472                 /* Configure VSC3316 crossbar switch */
 473                 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 474                 if (!ret) {
 475                         ret = vsc3316_config(VSC3316_TX_ADDRESS,
 476                                         vsc16_tx_sfp, num_vsc16_con);
 477                         if (ret)
 478                                 return ret;
 479                         ret = vsc3316_config(VSC3316_RX_ADDRESS,
 480                                         vsc16_rx_sfp, num_vsc16_con);
 481                         if (ret)
 482                                 return ret;
 483                 } else {
 484                         return ret;
 485                 }
 486                 break;
 487         default:
 488                 printf("WARNING:VSC crossbars programming not supported for:%x"
 489                                         " SerDes1 Protocol.\n", serdes1_prtcl);
 490                 return -1;
 491         }
 492
 493         switch (serdes2_prtcl) {
 494 #ifdef CONFIG_PPC_B4420
 495         case 0x9d:
 496 #endif
 497         case 0x9E:
 498         case 0x9A:
 499         case 0x98:
 500         case 0xb1:
 501         case 0xb2:
 502         case 0x48:
 503         case 0x49:
 504         case 0x4E:
 505         case 0x8C:
 506         case 0x8D:
 507         case 0x79:
 508         case 0x7A:
 509                 num_vsc08_con = NUM_CON_VSC3308;
 510                 /* Configure VSC3308 crossbar switch */
 511                 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
 512                 if (!ret) {
 513                         ret = vsc3308_config(VSC3308_TX_ADDRESS,
 514                                         vsc08_tx_amc, num_vsc08_con);
 515                         if (ret)
 516                                 return ret;
 517                         ret = vsc3308_config(VSC3308_RX_ADDRESS,
 518                                         vsc08_rx_amc, num_vsc08_con);
 519                         if (ret)
 520                                 return ret;
 521                 } else {
 522                         return ret;
 523                 }
 524                 break;
 525         default:
 526                 printf("WARNING:VSC crossbars programming not supported for: %x"
 527                                         " SerDes2 Protocol.\n", serdes2_prtcl);
 528                 return -1;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
 535 {
 536         u32 rst_err;
 537
 538         /* Steps For SerDes PLLs reset and reconfiguration
 539          * or PLL power-up procedure
 540          */
 541         debug("CALIBRATE PLL:%d\n", pll_num);
 542         clrbits_be32(&srds_regs->bank[pll_num].rstctl,
 543                         SRDS_RSTCTL_SDRST_B);
 544         udelay(10);
 545         clrbits_be32(&srds_regs->bank[pll_num].rstctl,
 546                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
 547         udelay(10);
 548         setbits_be32(&srds_regs->bank[pll_num].rstctl,
 549                         SRDS_RSTCTL_RST);
 550         setbits_be32(&srds_regs->bank[pll_num].rstctl,
 551                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
 552                 | SRDS_RSTCTL_SDRST_B));
 553
 554         udelay(20);
 555
 556         /* Check whether PLL has been locked or not */
 557         rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
 558                                 SRDS_RSTCTL_RSTERR;
 559         rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
 560         debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
 561         if (rst_err)
 562                 return rst_err;
 563
 564         return rst_err;
 565 }
 566
 567 static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
 568 {
 569         int ret = 0;
 570         u32 fcap, dcbias, bcap, pllcr1, pllcr0;
 571
 572         if (calibrate_pll(srds_regs, pll_num)) {
 573                 /* STEP 1 */
 574                 /* Read fcap, dcbias and bcap value */
 575                 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
 576                                 SRDS_PLLCR0_DCBIAS_OUT_EN);
 577                 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
 578                                         SRDS_PLLSR2_FCAP;
 579                 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
 580                 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
 581                                         SRDS_PLLSR2_BCAP_EN;
 582                 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
 583                 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
 584                                 SRDS_PLLCR0_DCBIAS_OUT_EN);
 585                 dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
 586                                         SRDS_PLLSR2_DCBIAS;
 587                 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
 588                 debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
 589                                         bcap, fcap, dcbias);
 590                 if (fcap == 0 && bcap == 1) {
 591                         /* Step 3 */
 592                         clrbits_be32(&srds_regs->bank[pll_num].rstctl,
 593                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
 594                                  | SRDS_RSTCTL_SDRST_B));
 595                         clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
 596                                         SRDS_PLLCR1_BCAP_EN);
 597                         setbits_be32(&srds_regs->bank[pll_num].pllcr1,
 598                                         SRDS_PLLCR1_BCAP_OVD);
 599                         if (calibrate_pll(srds_regs, pll_num)) {
 600                                 /*save the fcap, dcbias and bcap values*/
 601                                 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
 602                                                 SRDS_PLLCR0_DCBIAS_OUT_EN);
 603                                 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
 604                                         & SRDS_PLLSR2_FCAP;
 605                                 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
 606                                 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
 607                                         & SRDS_PLLSR2_BCAP_EN;
 608                                 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
 609                                 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
 610                                                 SRDS_PLLCR0_DCBIAS_OUT_EN);
 611                                 dcbias = in_be32
 612                                         (&srds_regs->bank[pll_num].pllsr2) &
 613                                                         SRDS_PLLSR2_DCBIAS;
 614                                 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
 615
 616                                 /* Step 4*/
 617                                 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
 618                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
 619                                  | SRDS_RSTCTL_SDRST_B));
 620                                 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
 621                                                 SRDS_PLLCR1_BYP_CAL);
 622                                 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
 623                                                 SRDS_PLLCR1_BCAP_EN);
 624                                 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
 625                                                 SRDS_PLLCR1_BCAP_OVD);
 626                                 /* change the fcap and dcbias to the saved
 627                                  * values from Step 3 */
 628                                 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
 629                                                         SRDS_PLLCR1_PLL_FCAP);
 630                                 pllcr1 = (in_be32
 631                                         (&srds_regs->bank[pll_num].pllcr1)|
 632                                         (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
 633                                 out_be32(&srds_regs->bank[pll_num].pllcr1,
 634                                                         pllcr1);
 635                                 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
 636                                                 SRDS_PLLCR0_DCBIAS_OVRD);
 637                                 pllcr0 = (in_be32
 638                                 (&srds_regs->bank[pll_num].pllcr0)|
 639                                 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
 640                                 out_be32(&srds_regs->bank[pll_num].pllcr0,
 641                                                         pllcr0);
 642                                 ret = calibrate_pll(srds_regs, pll_num);
 643                                 if (ret)
 644                                         return ret;
 645                         } else {
 646                                 goto out;
 647                         }
 648                 } else { /* Step 5 */
 649                         clrbits_be32(&srds_regs->bank[pll_num].rstctl,
 650                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
 651                                  | SRDS_RSTCTL_SDRST_B));
 652                         udelay(10);
 653                         /* Change the fcap, dcbias, and bcap to the
 654                          * values from Step 1 */
 655                         setbits_be32(&srds_regs->bank[pll_num].pllcr1,
 656                                         SRDS_PLLCR1_BYP_CAL);
 657                         clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
 658                                                 SRDS_PLLCR1_PLL_FCAP);
 659                         pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
 660                                 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
 661                         out_be32(&srds_regs->bank[pll_num].pllcr1,
 662                                                 pllcr1);
 663                         clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
 664                                                 SRDS_PLLCR0_DCBIAS_OVRD);
 665                         pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
 666                                 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
 667                         out_be32(&srds_regs->bank[pll_num].pllcr0,
 668                                                 pllcr0);
 669                         clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
 670                                         SRDS_PLLCR1_BCAP_EN);
 671                         setbits_be32(&srds_regs->bank[pll_num].pllcr1,
 672                                         SRDS_PLLCR1_BCAP_OVD);
 673                         ret = calibrate_pll(srds_regs, pll_num);
 674                         if (ret)
 675                                 return ret;
 676                 }
 677         }
 678 out:
 679         return 0;
 680 }
 681
 682 static int check_serdes_pll_locks(void)
 683 {
 684         serdes_corenet_t *srds1_regs =
 685                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 686         serdes_corenet_t *srds2_regs =
 687                 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
 688         int i, ret1, ret2;
 689
 690         debug("\nSerDes1 Lock check\n");
 691         for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 692                 ret1 = check_pll_locks(srds1_regs, i);
 693                 if (ret1) {
 694                         printf("SerDes1, PLL:%d didnt lock\n", i);
 695                         return ret1;
 696                 }
 697         }
 698         debug("\nSerDes2 Lock check\n");
 699         for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 700                 ret2 = check_pll_locks(srds2_regs, i);
 701                 if (ret2) {
 702                         printf("SerDes2, PLL:%d didnt lock\n", i);
 703                         return ret2;
 704                 }
 705         }
 706
 707         return 0;
 708 }
 709
 710 int config_serdes1_refclks(void)
 711 {
 712         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 713         serdes_corenet_t *srds_regs =
 714                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 715         u32 serdes1_prtcl, lane;
 716         unsigned int flag_sgmii_aurora_prtcl = 0;
 717         int i;
 718         int ret = 0;
 719
 720         serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
 721                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 722         if (!serdes1_prtcl) {
 723                 printf("SERDES1 is not enabled\n");
 724                 return -1;
 725         }
 726         serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 727         debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
 728
 729         /* To prevent generation of reset request from SerDes
 730          * while changing the refclks, By setting SRDS_RST_MSK bit,
 731          * SerDes reset event cannot cause a reset request
 732          */
 733         setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
 734
 735         /* Reconfigure IDT idt8t49n222a device for CPRI to work
 736          * For this SerDes1's Refclk1 and refclk2 need to be set
 737          * to 122.88MHz
 738          */
 739         switch (serdes1_prtcl) {
 740         case 0x29:
 741         case 0x2A:
 742         case 0x2C:
 743         case 0x2D:
 744         case 0x2E:
 745         case 0x01:
 746         case 0x02:
 747         case 0x04:
 748         case 0x05:
 749         case 0x06:
 750         case 0x07:
 751         case 0x08:
 752         case 0x09:
 753         case 0x0A:
 754         case 0x0B:
 755         case 0x0C:
 756         case 0x2F:
 757         case 0x30:
 758         case 0x32:
 759         case 0x33:
 760         case 0x34:
 761         case 0x39:
 762         case 0x3A:
 763         case 0x3C:
 764         case 0x3D:
 765         case 0x5C:
 766         case 0x5D:
 767                 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
 768                         " for srds_prctl:%x\n", serdes1_prtcl);
 769                 ret = select_i2c_ch_pca(I2C_CH_IDT);
 770                 if (!ret) {
 771                         ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
 772                                         SERDES_REFCLK_122_88,
 773                                         SERDES_REFCLK_122_88, 0);
 774                         if (ret) {
 775                                 printf("IDT8T49N222A configuration failed.\n");
 776                                 goto out;
 777                         } else
 778                                 debug("IDT8T49N222A configured.\n");
 779                 } else {
 780                         goto out;
 781                 }
 782                 select_i2c_ch_pca(I2C_CH_DEFAULT);
 783
 784                 /* Change SerDes1's Refclk1 to 125MHz for on board
 785                  * SGMIIs or Aurora to work
 786                  */
 787                 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 788                         enum srds_prtcl lane_prtcl = serdes_get_prtcl
 789                                                 (0, serdes1_prtcl, lane);
 790                         switch (lane_prtcl) {
 791                         case SGMII_FM1_DTSEC1:
 792                         case SGMII_FM1_DTSEC2:
 793                         case SGMII_FM1_DTSEC3:
 794                         case SGMII_FM1_DTSEC4:
 795                         case SGMII_FM1_DTSEC5:
 796                         case SGMII_FM1_DTSEC6:
 797                         case AURORA:
 798                                 flag_sgmii_aurora_prtcl++;
 799                                 break;
 800                         default:
 801                                 break;
 802                         }
 803                 }
 804
 805                 if (flag_sgmii_aurora_prtcl)
 806                         QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
 807
 808                 /* Steps For SerDes PLLs reset and reconfiguration after
 809                  * changing SerDes's refclks
 810                  */
 811                 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 812                         debug("For PLL%d reset and reconfiguration after"
 813                                " changing refclks\n", i+1);
 814                         clrbits_be32(&srds_regs->bank[i].rstctl,
 815                                         SRDS_RSTCTL_SDRST_B);
 816                         udelay(10);
 817                         clrbits_be32(&srds_regs->bank[i].rstctl,
 818                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
 819                         udelay(10);
 820                         setbits_be32(&srds_regs->bank[i].rstctl,
 821                                         SRDS_RSTCTL_RST);
 822                         setbits_be32(&srds_regs->bank[i].rstctl,
 823                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
 824                                 | SRDS_RSTCTL_SDRST_B));
 825                 }
 826                 break;
 827         default:
 828                 printf("WARNING:IDT8T49N222A configuration not"
 829                         " supported for:%x SerDes1 Protocol.\n",
 830                         serdes1_prtcl);
 831         }
 832
 833 out:
 834         /* Clearing SRDS_RST_MSK bit as now
 835          * SerDes reset event can cause a reset request
 836          */
 837         clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
 838         return ret;
 839 }
 840
 841 int config_serdes2_refclks(void)
 842 {
 843         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 844         serdes_corenet_t *srds2_regs =
 845                 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
 846         u32 serdes2_prtcl;
 847         int ret = 0;
 848         int i;
 849
 850         serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
 851                         FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 852         if (!serdes2_prtcl) {
 853                 debug("SERDES2 is not enabled\n");
 854                 return -ENODEV;
 855         }
 856         serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 857         debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
 858
 859         /* To prevent generation of reset request from SerDes
 860          * while changing the refclks, By setting SRDS_RST_MSK bit,
 861          * SerDes reset event cannot cause a reset request
 862          */
 863         setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
 864
 865         /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
 866          * For this SerDes2's Refclk1 need to be set to 100MHz
 867          */
 868         switch (serdes2_prtcl) {
 869 #ifdef CONFIG_PPC_B4420
 870         case 0x9d:
 871 #endif
 872         case 0x9E:
 873         case 0x9A:
 874                 /* fallthrough */
 875         case 0xb1:
 876         case 0xb2:
 877                 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
 878                         serdes2_prtcl);
 879                 ret = select_i2c_ch_pca(I2C_CH_IDT);
 880                 if (!ret) {
 881                         ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
 882                                         SERDES_REFCLK_100,
 883                                         SERDES_REFCLK_156_25, 0);
 884                         if (ret) {
 885                                 printf("IDT8T49N222A configuration failed.\n");
 886                                 goto out;
 887                         } else
 888                                 debug("IDT8T49N222A configured.\n");
 889                 } else {
 890                         goto out;
 891                 }
 892                 select_i2c_ch_pca(I2C_CH_DEFAULT);
 893
 894                 /* Steps For SerDes PLLs reset and reconfiguration after
 895                  * changing SerDes's refclks
 896                  */
 897                 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 898                         clrbits_be32(&srds2_regs->bank[i].rstctl,
 899                                         SRDS_RSTCTL_SDRST_B);
 900                         udelay(10);
 901                         clrbits_be32(&srds2_regs->bank[i].rstctl,
 902                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
 903                         udelay(10);
 904                         setbits_be32(&srds2_regs->bank[i].rstctl,
 905                                         SRDS_RSTCTL_RST);
 906                         setbits_be32(&srds2_regs->bank[i].rstctl,
 907                                 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
 908                                 | SRDS_RSTCTL_SDRST_B));
 909
 910                         udelay(10);
 911                 }
 912                 break;
 913         default:
 914                 printf("IDT configuration not supported for:%x S2 Protocol.\n",
 915                         serdes2_prtcl);
 916         }
 917
 918 out:
 919         /* Clearing SRDS_RST_MSK bit as now
 920          * SerDes reset event can cause a reset request
 921          */
 922         clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
 923         return ret;
 924 }
 925
 926 int board_early_init_r(void)
 927 {
 928         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 929         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 930         int ret;
 931         u32 svr = SVR_SOC_VER(get_svr());
 932
 933         /* Create law for MAPLE only for personalities having MAPLE */
 934         if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
 935             (svr == SVR_B4420) || (svr == SVR_B4220)) {
 936                 set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
 937                              LAW_TRGT_IF_MAPLE);
 938         }
 939
 940         /*
 941          * Remap Boot flash + PROMJET region to caching-inhibited
 942          * so that flash can be erased properly.
 943          */
 944
 945         /* Flush d-cache and invalidate i-cache of any FLASH data */
 946         flush_dcache();
 947         invalidate_icache();
 948
 949         if (flash_esel == -1) {
 950                 /* very unlikely unless something is messed up */
 951                 puts("Error: Could not find TLB for FLASH BASE\n");
 952                 flash_esel = 2; /* give our best effort to continue */
 953         } else {
 954                 /* invalidate existing TLB entry for flash + promjet */
 955                 disable_tlb(flash_esel);
 956         }
 957
 958         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 959                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 960                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 961
 962         set_liodns();
 963 #ifdef CONFIG_SYS_DPAA_QBMAN
 964         setup_portals();
 965 #endif
 966         /*
 967          * Adjust core voltage according to voltage ID
 968          * This function changes I2C mux to channel 2.
 969          */
 970         if (adjust_vdd(0) < 0)
 971                 printf("Warning: Adjusting core voltage failed\n");
 972
 973         /* SerDes1 refclks need to be set again, as default clks
 974          * are not suitable for CPRI and onboard SGMIIs to work
 975          * simultaneously.
 976          * This function will set SerDes1's Refclk1 and refclk2
 977          * as per SerDes1 protocols
 978          */
 979         if (config_serdes1_refclks())
 980                 printf("SerDes1 Refclks couldn't set properly.\n");
 981         else
 982                 printf("SerDes1 Refclks have been set.\n");
 983
 984         /* SerDes2 refclks need to be set again, as default clks
 985          * are not suitable for PCIe SATA to work
 986          * This function will set SerDes2's Refclk1 and refclk2
 987          * for SerDes2 protocols having PCIe in them
 988          * for PCIe SATA to work
 989          */
 990         ret = config_serdes2_refclks();
 991         if (!ret)
 992                 printf("SerDes2 Refclks have been set.\n");
 993         else if (ret == -ENODEV)
 994                 printf("SerDes disable, Refclks couldn't change.\n");
 995         else
 996                 printf("SerDes2 Refclk reconfiguring failed.\n");
 997
 998 #if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
 999                         defined(CONFIG_SYS_FSL_ERRATUM_A006475)
1000         /* Rechecking the SerDes locks after all SerDes configurations
1001          * are done, As SerDes PLLs may not lock reliably at 5 G VCO
1002          * and at cold temperatures.
1003          * Following sequence ensure the proper locking of SerDes PLLs.
1004          */
1005         if (SVR_MAJ(get_svr()) == 1) {
1006                 if (check_serdes_pll_locks())
1007                         printf("SerDes plls still not locked properly.\n");
1008                 else
1009                         printf("SerDes plls have been locked well.\n");
1010         }
1011 #endif
1012
1013         /* Configure VSC3316 and VSC3308 crossbar switches */
1014         if (configure_vsc3316_3308())
1015                 printf("VSC:failed to configure VSC3316/3308.\n");
1016         else
1017                 printf("VSC:VSC3316/3308 successfully configured.\n");
1018
1019         select_i2c_ch_pca(I2C_CH_DEFAULT);
1020
1021         return 0;
1022 }
1023
1024 unsigned long get_board_sys_clk(void)
1025 {
1026         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
1027
1028         switch ((sysclk_conf & 0x0C) >> 2) {
1029         case QIXIS_CLK_100:
1030                 return 100000000;
1031         case QIXIS_CLK_125:
1032                 return 125000000;
1033         case QIXIS_CLK_133:
1034                 return 133333333;
1035         }
1036         return 66666666;
1037 }
1038
1039 unsigned long get_board_ddr_clk(void)
1040 {
1041         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
1042
1043         switch (ddrclk_conf & 0x03) {
1044         case QIXIS_CLK_100:
1045                 return 100000000;
1046         case QIXIS_CLK_125:
1047                 return 125000000;
1048         case QIXIS_CLK_133:
1049                 return 133333333;
1050         }
1051         return 66666666;
1052 }
1053
1054 static int serdes_refclock(u8 sw, u8 sdclk)
1055 {
1056         unsigned int clock;
1057         int ret = -1;
1058         u8 brdcfg4;
1059
1060         if (sdclk == 1) {
1061                 brdcfg4 = QIXIS_READ(brdcfg[4]);
1062                 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
1063                         return SRDS_PLLCR0_RFCK_SEL_125;
1064                 else
1065                         clock = (sw >> 5) & 7;
1066         } else
1067                 clock = (sw >> 6) & 3;
1068
1069         switch (clock) {
1070         case 0:
1071                 ret = SRDS_PLLCR0_RFCK_SEL_100;
1072                 break;
1073         case 1:
1074                 ret = SRDS_PLLCR0_RFCK_SEL_125;
1075                 break;
1076         case 2:
1077                 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
1078                 break;
1079         case 3:
1080                 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
1081                 break;
1082         case 4:
1083         case 5:
1084         case 6:
1085                 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
1086                 break;
1087         default:
1088                 ret = -1;
1089                 break;
1090         }
1091
1092         return ret;
1093 }
1094
1095 #define NUM_SRDS_BANKS  2
1096
1097 int misc_init_r(void)
1098 {
1099         u8 sw;
1100         serdes_corenet_t *srds_regs =
1101                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
1102         u32 actual[NUM_SRDS_BANKS];
1103         unsigned int i;
1104         int clock;
1105
1106         sw = QIXIS_READ(brdcfg[2]);
1107         clock = serdes_refclock(sw, 1);
1108         if (clock >= 0)
1109                 actual[0] = clock;
1110         else
1111                 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
1112
1113         sw = QIXIS_READ(brdcfg[4]);
1114         clock = serdes_refclock(sw, 2);
1115         if (clock >= 0)
1116                 actual[1] = clock;
1117         else
1118                 printf("Warning: SDREFCLK2 switch setting unsupported\n");
1119
1120         for (i = 0; i < NUM_SRDS_BANKS; i++) {
1121                 u32 pllcr0 = srds_regs->bank[i].pllcr0;
1122                 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
1123                 if (expected != actual[i]) {
1124                         printf("Warning: SERDES bank %u expects reference clock"
1125                                " %sMHz, but actual is %sMHz\n", i + 1,
1126                                serdes_clock_to_string(expected),
1127                                serdes_clock_to_string(actual[i]));
1128                 }
1129         }
1130
1131         return 0;
1132 }
1133
1134 int ft_board_setup(void *blob, bd_t *bd)
1135 {
1136         phys_addr_t base;
1137         phys_size_t size;
1138
1139         ft_cpu_setup(blob, bd);
1140
1141         base = getenv_bootm_low();
1142         size = getenv_bootm_size();
1143
1144         fdt_fixup_memory(blob, (u64)base, (u64)size);
1145
1146 #ifdef CONFIG_PCI
1147         pci_of_setup(blob, bd);
1148 #endif
1149
1150         fdt_fixup_liodn(blob);
1151
1152 #ifdef CONFIG_HAS_FSL_DR_USB
1153         fdt_fixup_dr_usb(blob, bd);
1154 #endif
1155
1156 #ifdef CONFIG_SYS_DPAA_FMAN
1157         fdt_fixup_fman_ethernet(blob);
1158         fdt_fixup_board_enet(blob);
1159 #endif
1160
1161         return 0;
1162 }
1163
1164 /*
1165  * Dump board switch settings.
1166  * The bits that cannot be read/sampled via some FPGA or some
1167  * registers, they will be displayed as
1168  * underscore in binary format. mask[] has those bits.
1169  * Some bits are calculated differently than the actual switches
1170  * if booting with overriding by FPGA.
1171  */
1172 void qixis_dump_switch(void)
1173 {
1174         int i;
1175         u8 sw[5];
1176
1177         /*
1178          * Any bit with 1 means that bit cannot be reverse engineered.
1179          * It will be displayed as _ in binary format.
1180          */
1181         static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
1182         char buf[10];
1183         u8 brdcfg[16], dutcfg[16];
1184
1185         for (i = 0; i < 16; i++) {
1186                 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
1187                 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
1188         }
1189
1190         sw[0] = ((brdcfg[0] & 0x0f) << 4)       | \
1191                 (brdcfg[9] & 0x08);
1192         sw[1] = ((dutcfg[1] & 0x01) << 7)       | \
1193                 ((dutcfg[2] & 0x07) << 4)       | \
1194                 ((dutcfg[6] & 0x10) >> 1)       | \
1195                 ((dutcfg[6] & 0x80) >> 5)       | \
1196                 ((dutcfg[1] & 0x40) >> 5)       | \
1197                 (dutcfg[6] & 0x01);
1198         sw[2] = dutcfg[0];
1199         sw[3] = 0;
1200         sw[4] = ((brdcfg[1] & 0x30) << 2)       | \
1201                 ((brdcfg[1] & 0xc0) >> 2)       | \
1202                 (brdcfg[1] & 0x0f);
1203
1204         puts("DIP switch settings:\n");
1205         for (i = 0; i < 5; i++) {
1206                 printf("SW%d         = 0b%s (0x%02x)\n",
1207                         i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
1208         }
1209 }