2 * pci.c -- esd VME8349 PCI board support.
3 * Copyright (c) 2006 Wind River Systems, Inc.
4 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 esd gmbh.
7 * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
9 * Based on MPC8349 PCI support but w/o PIB related code.
11 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/fsl_i2c.h>
21 #include "vme8349pin.h"
23 static struct pci_region pci1_regions[] = {
25 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
26 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
27 size: CONFIG_SYS_PCI1_MEM_SIZE,
28 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
31 bus_start: CONFIG_SYS_PCI1_IO_BASE,
32 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
33 size: CONFIG_SYS_PCI1_IO_SIZE,
37 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
38 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
39 size: CONFIG_SYS_PCI1_MMIO_SIZE,
47 * NOTICE: PCI2 is not supported. There is only one
48 * physical PCI slot on the board.
54 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
55 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
56 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
57 struct pci_region *reg[] = { pci1_regions };
62 /* Read the PCI_M66EN jumper setting */
63 if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) ||
64 (i2c_read(0x38 , 0, 0, ®8, 1) == 0)) {
66 clk->occr = 0xff000000; /* 66 MHz PCI */
67 printf("PCI: 66MHz\n");
69 clk->occr = 0xffff0003; /* 33 MHz PCI */
70 printf("PCI: 33MHz\n");
72 if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
75 clk->occr = 0xffff0003; /* 33 MHz PCI */
76 printf("PCI: 33MHz (I2C read failed)\n");
81 * Assert/deassert VME reset
83 clrsetbits_be32(&immr->gpio[1].dat,
84 GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
85 GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
86 setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
87 GPIO2_TSI_POWERUP_RESET_N |
90 clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
92 setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
94 setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
96 clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
98 /* Configure PCI Local Access Windows */
99 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
100 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
102 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
103 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
108 mpc83xx_pci_init(1, reg);
111 * Release PCI RST Output signal
113 out_be32(&immr->pci_ctrl[0].gcr, 0);
115 out_be32(&immr->pci_ctrl[0].gcr, 1);