board/engicam/common/spl.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <spl.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-ddr.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/arch/sys_proto.h>
  22
  23 #include <asm/mach-imx/iomux-v3.h>
  24 #include <asm/mach-imx/video.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  29         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  30         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  31
  32 static iomux_v3_cfg_t const uart_pads[] = {
  33 #ifdef CONFIG_MX6QDL
  34         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  35         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  36 #elif CONFIG_MX6UL
  37         IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
  38         IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
  39 #endif
  40 };
  41
  42 #ifdef CONFIG_SPL_OS_BOOT
  43 int spl_start_uboot(void)
  44 {
  45         /* break into full u-boot on 'c' */
  46         if (serial_tstc() && serial_getc() == 'c')
  47                 return 1;
  48
  49         return 0;
  50 }
  51 #endif
  52
  53 #ifdef CONFIG_MX6QDL
  54 /*
  55  * Driving strength:
  56  *   0x30 == 40 Ohm
  57  *   0x28 == 48 Ohm
  58  */
  59 #define IMX6DQ_DRIVE_STRENGTH           0x30
  60 #define IMX6SDL_DRIVE_STRENGTH          0x28
  61
  62 /* configure MX6Q/DUAL mmdc DDR io registers */
  63 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  64         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  65         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  66         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  67         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  68         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  69         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  70         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  71         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  72         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  73         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  74         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  75         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  76         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  77         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  78         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  79         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  80         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  81         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  82         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  83         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  84         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  85         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  86         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  87         .dram_sdba2 = 0x00000000,
  88         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  89         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  90 };
  91
  92 /* configure MX6Q/DUAL mmdc GRP io registers */
  93 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  94         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  95         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  96         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  97         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  98         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  99         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
 100         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
 101         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
 102         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
 103         .grp_ddrmode_ctl = 0x00020000,
 104         .grp_ddrpke = 0x00000000,
 105         .grp_ddrmode = 0x00020000,
 106         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
 107         .grp_ddr_type = 0x000c0000,
 108 };
 109
 110 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 111 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 112         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
 113         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
 114         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
 115         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
 116         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
 117         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
 118         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 119         .dram_sdba2 = 0x00000000,
 120         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 121         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 122         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 123         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 124         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 125         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 126         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 127         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 128         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 129         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 130         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 131         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 132         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 133         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 134         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 135         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 136         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 137         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 138 };
 139
 140 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 141 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 142         .grp_ddr_type = 0x000c0000,
 143         .grp_ddrmode_ctl = 0x00020000,
 144         .grp_ddrpke = 0x00000000,
 145         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 146         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 147         .grp_ddrmode = 0x00020000,
 148         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 149         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 150         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 151         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 152         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 153         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 154         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 155         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 156 };
 157
 158 /* mt41j256 */
 159 static struct mx6_ddr3_cfg mt41j256 = {
 160         .mem_speed = 1066,
 161         .density = 2,
 162         .width = 16,
 163         .banks = 8,
 164         .rowaddr = 13,
 165         .coladdr = 10,
 166         .pagesz = 2,
 167         .trcd = 1375,
 168         .trcmin = 4875,
 169         .trasmin = 3500,
 170         .SRT = 0,
 171 };
 172
 173 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 174         .p0_mpwldectrl0 = 0x000E0009,
 175         .p0_mpwldectrl1 = 0x0018000E,
 176         .p1_mpwldectrl0 = 0x00000007,
 177         .p1_mpwldectrl1 = 0x00000000,
 178         .p0_mpdgctrl0 = 0x43280334,
 179         .p0_mpdgctrl1 = 0x031C0314,
 180         .p1_mpdgctrl0 = 0x4318031C,
 181         .p1_mpdgctrl1 = 0x030C0258,
 182         .p0_mprddlctl = 0x3E343A40,
 183         .p1_mprddlctl = 0x383C3844,
 184         .p0_mpwrdlctl = 0x40404440,
 185         .p1_mpwrdlctl = 0x4C3E4446,
 186 };
 187
 188 /* DDR 64bit */
 189 static struct mx6_ddr_sysinfo mem_q = {
 190         .ddr_type       = DDR_TYPE_DDR3,
 191         .dsize          = 2,
 192         .cs1_mirror     = 0,
 193         /* config for full 4GB range so that get_mem_size() works */
 194         .cs_density     = 32,
 195         .ncs            = 1,
 196         .bi_on          = 1,
 197         .rtt_nom        = 2,
 198         .rtt_wr         = 2,
 199         .ralat          = 5,
 200         .walat          = 0,
 201         .mif3_mode      = 3,
 202         .rst_to_cke     = 0x23,
 203         .sde_to_rst     = 0x10,
 204 };
 205
 206 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 207         .p0_mpwldectrl0 = 0x001F0024,
 208         .p0_mpwldectrl1 = 0x00110018,
 209         .p1_mpwldectrl0 = 0x001F0024,
 210         .p1_mpwldectrl1 = 0x00110018,
 211         .p0_mpdgctrl0 = 0x4230022C,
 212         .p0_mpdgctrl1 = 0x02180220,
 213         .p1_mpdgctrl0 = 0x42440248,
 214         .p1_mpdgctrl1 = 0x02300238,
 215         .p0_mprddlctl = 0x44444A48,
 216         .p1_mprddlctl = 0x46484A42,
 217         .p0_mpwrdlctl = 0x38383234,
 218         .p1_mpwrdlctl = 0x3C34362E,
 219 };
 220
 221 /* DDR 64bit 1GB */
 222 static struct mx6_ddr_sysinfo mem_dl = {
 223         .dsize          = 2,
 224         .cs1_mirror     = 0,
 225         /* config for full 4GB range so that get_mem_size() works */
 226         .cs_density     = 32,
 227         .ncs            = 1,
 228         .bi_on          = 1,
 229         .rtt_nom        = 1,
 230         .rtt_wr         = 1,
 231         .ralat          = 5,
 232         .walat          = 0,
 233         .mif3_mode      = 3,
 234         .rst_to_cke     = 0x23,
 235         .sde_to_rst     = 0x10,
 236 };
 237
 238 /* DDR 32bit 512MB */
 239 static struct mx6_ddr_sysinfo mem_s = {
 240         .dsize          = 1,
 241         .cs1_mirror     = 0,
 242         /* config for full 4GB range so that get_mem_size() works */
 243         .cs_density     = 32,
 244         .ncs            = 1,
 245         .bi_on          = 1,
 246         .rtt_nom        = 1,
 247         .rtt_wr         = 1,
 248         .ralat          = 5,
 249         .walat          = 0,
 250         .mif3_mode      = 3,
 251         .rst_to_cke     = 0x23,
 252         .sde_to_rst     = 0x10,
 253 };
 254 #endif /* CONFIG_MX6QDL */
 255
 256 #ifdef CONFIG_MX6UL
 257 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 258         .grp_addds = 0x00000030,
 259         .grp_ddrmode_ctl = 0x00020000,
 260         .grp_b0ds = 0x00000030,
 261         .grp_ctlds = 0x00000030,
 262         .grp_b1ds = 0x00000030,
 263         .grp_ddrpke = 0x00000000,
 264         .grp_ddrmode = 0x00020000,
 265         .grp_ddr_type = 0x000c0000,
 266 };
 267
 268 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 269         .dram_dqm0 = 0x00000030,
 270         .dram_dqm1 = 0x00000030,
 271         .dram_ras = 0x00000030,
 272         .dram_cas = 0x00000030,
 273         .dram_odt0 = 0x00000030,
 274         .dram_odt1 = 0x00000030,
 275         .dram_sdba2 = 0x00000000,
 276         .dram_sdclk_0 = 0x00000008,
 277         .dram_sdqs0 = 0x00000038,
 278         .dram_sdqs1 = 0x00000030,
 279         .dram_reset = 0x00000030,
 280 };
 281
 282 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 283         .p0_mpwldectrl0 = 0x00070007,
 284         .p0_mpdgctrl0 = 0x41490145,
 285         .p0_mprddlctl = 0x40404546,
 286         .p0_mpwrdlctl = 0x4040524D,
 287 };
 288
 289 struct mx6_ddr_sysinfo ddr_sysinfo = {
 290         .dsize = 0,
 291         .cs_density = 20,
 292         .ncs = 1,
 293         .cs1_mirror = 0,
 294         .rtt_wr = 2,
 295         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 296         .walat = 1,             /* Write additional latency */
 297         .ralat = 5,             /* Read additional latency */
 298         .mif3_mode = 3,         /* Command prediction working mode */
 299         .bi_on = 1,             /* Bank interleaving enabled */
 300         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 301         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 302         .ddr_type = DDR_TYPE_DDR3,
 303 };
 304
 305 static struct mx6_ddr3_cfg mem_ddr = {
 306         .mem_speed = 800,
 307         .density = 4,
 308         .width = 16,
 309         .banks = 8,
 310 #ifdef TARGET_MX6UL_ISIOT
 311         .rowaddr = 15,
 312 #else
 313         .rowaddr = 13,
 314 #endif
 315         .coladdr = 10,
 316         .pagesz = 2,
 317         .trcd = 1375,
 318         .trcmin = 4875,
 319         .trasmin = 3500,
 320 };
 321 #endif /* CONFIG_MX6UL */
 322
 323 static void ccgr_init(void)
 324 {
 325         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 326
 327 #ifdef CONFIG_MX6QDL
 328         writel(0x00003F3F, &ccm->CCGR0);
 329         writel(0x0030FC00, &ccm->CCGR1);
 330         writel(0x000FC000, &ccm->CCGR2);
 331         writel(0x3F300000, &ccm->CCGR3);
 332         writel(0xFF00F300, &ccm->CCGR4);
 333         writel(0x0F0000C3, &ccm->CCGR5);
 334         writel(0x000003CC, &ccm->CCGR6);
 335 #elif CONFIG_MX6UL
 336         writel(0x00c03f3f, &ccm->CCGR0);
 337         writel(0xfcffff00, &ccm->CCGR1);
 338         writel(0x0cffffcc, &ccm->CCGR2);
 339         writel(0x3f3c3030, &ccm->CCGR3);
 340         writel(0xff00fffc, &ccm->CCGR4);
 341         writel(0x033f30ff, &ccm->CCGR5);
 342         writel(0x00c00fff, &ccm->CCGR6);
 343 #endif
 344 }
 345
 346 static void spl_dram_init(void)
 347 {
 348 #ifdef CONFIG_MX6QDL
 349         if (is_mx6solo()) {
 350                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 351                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 352         } else if (is_mx6dl()) {
 353                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 354                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 355         } else if (is_mx6dq()) {
 356                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 357                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 358         }
 359 #elif CONFIG_MX6UL
 360         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 361         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 362 #endif
 363
 364         udelay(100);
 365 }
 366
 367 void board_init_f(ulong dummy)
 368 {
 369         ccgr_init();
 370
 371         /* setup AIPS and disable watchdog */
 372         arch_cpu_init();
 373
 374         gpr_init();
 375
 376         /* iomux */
 377         SETUP_IOMUX_PADS(uart_pads);
 378
 379         /* setup GP timer */
 380         timer_init();
 381
 382         /* UART clocks enabled and gd valid - init serial console */
 383         preloader_console_init();
 384
 385         /* DDR initialization */
 386         spl_dram_init();
 387 }