board/engicam/common/spl.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <spl.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-ddr.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/arch/sys_proto.h>
  22
  23 #include <asm/imx-common/iomux-v3.h>
  24 #include <asm/imx-common/video.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  29         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  30         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  31
  32 static iomux_v3_cfg_t const uart4_pads[] = {
  33         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  34         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  35 };
  36
  37 /*
  38  * Driving strength:
  39  *   0x30 == 40 Ohm
  40  *   0x28 == 48 Ohm
  41  */
  42 #define IMX6DQ_DRIVE_STRENGTH           0x30
  43 #define IMX6SDL_DRIVE_STRENGTH          0x28
  44
  45 /* configure MX6Q/DUAL mmdc DDR io registers */
  46 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  47         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  48         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  49         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  50         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  51         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  52         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  53         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  54         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  55         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  56         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  57         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  58         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  59         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  60         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  61         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  62         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  63         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  64         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  65         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  66         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  67         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  68         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  69         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  70         .dram_sdba2 = 0x00000000,
  71         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  72         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  73 };
  74
  75 /* configure MX6Q/DUAL mmdc GRP io registers */
  76 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  77         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  78         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  79         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  80         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  81         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  82         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  83         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  84         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  85         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  86         .grp_ddrmode_ctl = 0x00020000,
  87         .grp_ddrpke = 0x00000000,
  88         .grp_ddrmode = 0x00020000,
  89         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  90         .grp_ddr_type = 0x000c0000,
  91 };
  92
  93 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  94 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  95         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  96         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  97         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  98         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  99         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
 100         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
 101         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 102         .dram_sdba2 = 0x00000000,
 103         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 104         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 105         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 106         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 107         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 108         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 109         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 110         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 111         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 112         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 113         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 114         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 115         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 116         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 117         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 118         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 119         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 120         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 121 };
 122
 123 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 124 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 125         .grp_ddr_type = 0x000c0000,
 126         .grp_ddrmode_ctl = 0x00020000,
 127         .grp_ddrpke = 0x00000000,
 128         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 129         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 130         .grp_ddrmode = 0x00020000,
 131         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 132         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 133         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 134         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 135         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 136         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 137         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 138         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 139 };
 140
 141 /* mt41j256 */
 142 static struct mx6_ddr3_cfg mt41j256 = {
 143         .mem_speed = 1066,
 144         .density = 2,
 145         .width = 16,
 146         .banks = 8,
 147         .rowaddr = 13,
 148         .coladdr = 10,
 149         .pagesz = 2,
 150         .trcd = 1375,
 151         .trcmin = 4875,
 152         .trasmin = 3500,
 153         .SRT = 0,
 154 };
 155
 156 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 157         .p0_mpwldectrl0 = 0x000E0009,
 158         .p0_mpwldectrl1 = 0x0018000E,
 159         .p1_mpwldectrl0 = 0x00000007,
 160         .p1_mpwldectrl1 = 0x00000000,
 161         .p0_mpdgctrl0 = 0x43280334,
 162         .p0_mpdgctrl1 = 0x031C0314,
 163         .p1_mpdgctrl0 = 0x4318031C,
 164         .p1_mpdgctrl1 = 0x030C0258,
 165         .p0_mprddlctl = 0x3E343A40,
 166         .p1_mprddlctl = 0x383C3844,
 167         .p0_mpwrdlctl = 0x40404440,
 168         .p1_mpwrdlctl = 0x4C3E4446,
 169 };
 170
 171 /* DDR 64bit */
 172 static struct mx6_ddr_sysinfo mem_q = {
 173         .ddr_type       = DDR_TYPE_DDR3,
 174         .dsize          = 2,
 175         .cs1_mirror     = 0,
 176         /* config for full 4GB range so that get_mem_size() works */
 177         .cs_density     = 32,
 178         .ncs            = 1,
 179         .bi_on          = 1,
 180         .rtt_nom        = 2,
 181         .rtt_wr         = 2,
 182         .ralat          = 5,
 183         .walat          = 0,
 184         .mif3_mode      = 3,
 185         .rst_to_cke     = 0x23,
 186         .sde_to_rst     = 0x10,
 187 };
 188
 189 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 190         .p0_mpwldectrl0 = 0x001F0024,
 191         .p0_mpwldectrl1 = 0x00110018,
 192         .p1_mpwldectrl0 = 0x001F0024,
 193         .p1_mpwldectrl1 = 0x00110018,
 194         .p0_mpdgctrl0 = 0x4230022C,
 195         .p0_mpdgctrl1 = 0x02180220,
 196         .p1_mpdgctrl0 = 0x42440248,
 197         .p1_mpdgctrl1 = 0x02300238,
 198         .p0_mprddlctl = 0x44444A48,
 199         .p1_mprddlctl = 0x46484A42,
 200         .p0_mpwrdlctl = 0x38383234,
 201         .p1_mpwrdlctl = 0x3C34362E,
 202 };
 203
 204 /* DDR 64bit 1GB */
 205 static struct mx6_ddr_sysinfo mem_dl = {
 206         .dsize          = 2,
 207         .cs1_mirror     = 0,
 208         /* config for full 4GB range so that get_mem_size() works */
 209         .cs_density     = 32,
 210         .ncs            = 1,
 211         .bi_on          = 1,
 212         .rtt_nom        = 1,
 213         .rtt_wr         = 1,
 214         .ralat          = 5,
 215         .walat          = 0,
 216         .mif3_mode      = 3,
 217         .rst_to_cke     = 0x23,
 218         .sde_to_rst     = 0x10,
 219 };
 220
 221 /* DDR 32bit 512MB */
 222 static struct mx6_ddr_sysinfo mem_s = {
 223         .dsize          = 1,
 224         .cs1_mirror     = 0,
 225         /* config for full 4GB range so that get_mem_size() works */
 226         .cs_density     = 32,
 227         .ncs            = 1,
 228         .bi_on          = 1,
 229         .rtt_nom        = 1,
 230         .rtt_wr         = 1,
 231         .ralat          = 5,
 232         .walat          = 0,
 233         .mif3_mode      = 3,
 234         .rst_to_cke     = 0x23,
 235         .sde_to_rst     = 0x10,
 236 };
 237
 238 static void ccgr_init(void)
 239 {
 240         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 241
 242         writel(0x00003F3F, &ccm->CCGR0);
 243         writel(0x0030FC00, &ccm->CCGR1);
 244         writel(0x000FC000, &ccm->CCGR2);
 245         writel(0x3F300000, &ccm->CCGR3);
 246         writel(0xFF00F300, &ccm->CCGR4);
 247         writel(0x0F0000C3, &ccm->CCGR5);
 248         writel(0x000003CC, &ccm->CCGR6);
 249 }
 250
 251 static void gpr_init(void)
 252 {
 253         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 254
 255         /* enable AXI cache for VDOA/VPU/IPU */
 256         writel(0xF00000CF, &iomux->gpr[4]);
 257         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 258         writel(0x007F007F, &iomux->gpr[6]);
 259         writel(0x007F007F, &iomux->gpr[7]);
 260 }
 261
 262 static void spl_dram_init(void)
 263 {
 264         if (is_mx6solo()) {
 265                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 266                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 267         } else if (is_mx6dl()) {
 268                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 269                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 270         } else if (is_mx6dq()) {
 271                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 272                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 273         }
 274
 275         udelay(100);
 276 }
 277
 278 void board_init_f(ulong dummy)
 279 {
 280         ccgr_init();
 281
 282         /* setup AIPS and disable watchdog */
 283         arch_cpu_init();
 284
 285         gpr_init();
 286
 287         /* iomux */
 288         SETUP_IOMUX_PADS(uart4_pads);
 289
 290         /* setup GP timer */
 291         timer_init();
 292
 293         /* UART clocks enabled and gd valid - init serial console */
 294         preloader_console_init();
 295
 296         /* DDR initialization */
 297         spl_dram_init();
 298
 299         /* Clear the BSS. */
 300         memset(__bss_start, 0, __bss_end - __bss_start);
 301
 302         /* load/boot image from boot device */
 303         board_init_r(NULL, 0);
 304 }