board/engicam/common/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Amarula Solutions B.V.
   4  * Copyright (C) 2016 Engicam S.r.l.
   5  * Author: Jagan Teki <jagan@amarulasolutions.com>
   6  */
   7
   8 #include <common.h>
   9 #include <image.h>
  10 #include <init.h>
  11 #include <serial.h>
  12 #include <spl.h>
  13 #include <linux/delay.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/gpio.h>
  17 #include <linux/sizes.h>
  18
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <asm/arch/iomux.h>
  22 #include <asm/arch/mx6-ddr.h>
  23 #include <asm/arch/mx6-pins.h>
  24 #include <asm/arch/sys_proto.h>
  25
  26 #include <asm/mach-imx/iomux-v3.h>
  27 #include <asm/mach-imx/video.h>
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  30         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  31         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 static iomux_v3_cfg_t const uart_pads[] = {
  34 #ifdef CONFIG_MX6QDL
  35         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  36         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  37 #elif CONFIG_MX6UL
  38         IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
  39         IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
  40 #endif
  41 };
  42
  43 #ifdef CONFIG_SPL_LOAD_FIT
  44 int board_fit_config_name_match(const char *name)
  45 {
  46         if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
  47                 return 0;
  48         else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
  49                 return 0;
  50         else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi"))
  51                 return 0;
  52         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
  53                 return 0;
  54         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
  55                 return 0;
  56         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi"))
  57                 return 0;
  58         else
  59                 return -1;
  60 }
  61 #endif
  62
  63 #ifdef CONFIG_ENV_IS_IN_MMC
  64 void board_boot_order(u32 *spl_boot_list)
  65 {
  66         u32 bmode = imx6_src_get_boot_mode();
  67         u8 boot_dev = BOOT_DEVICE_MMC1;
  68
  69         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
  70         case IMX6_BMODE_SD:
  71         case IMX6_BMODE_ESD:
  72                 /* SD/eSD - BOOT_DEVICE_MMC1 */
  73                 break;
  74         case IMX6_BMODE_MMC:
  75         case IMX6_BMODE_EMMC:
  76                 /* MMC/eMMC */
  77                 boot_dev = BOOT_DEVICE_MMC2;
  78                 break;
  79         default:
  80                 /* Default - BOOT_DEVICE_MMC1 */
  81                 printf("Wrong board boot order\n");
  82                 break;
  83         }
  84
  85         spl_boot_list[0] = boot_dev;
  86 }
  87 #endif
  88
  89 #ifdef CONFIG_SPL_OS_BOOT
  90 int spl_start_uboot(void)
  91 {
  92         /* break into full u-boot on 'c' */
  93         if (serial_tstc() && serial_getc() == 'c')
  94                 return 1;
  95
  96         return 0;
  97 }
  98 #endif
  99
 100 #ifdef CONFIG_MX6QDL
 101 /*
 102  * Driving strength:
 103  *   0x30 == 40 Ohm
 104  *   0x28 == 48 Ohm
 105  */
 106 #define IMX6DQ_DRIVE_STRENGTH           0x30
 107 #define IMX6SDL_DRIVE_STRENGTH          0x28
 108
 109 /* configure MX6Q/DUAL mmdc DDR io registers */
 110 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 111         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
 112         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
 113         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
 114         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
 115         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
 116         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
 117         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
 118         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
 119         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
 120         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
 121         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
 122         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
 123         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
 124         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
 125         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
 126         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
 127         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
 128         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
 129         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
 130         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
 131         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
 132         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
 133         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
 134         .dram_sdba2 = 0x00000000,
 135         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
 136         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
 137 };
 138
 139 /* configure MX6Q/DUAL mmdc GRP io registers */
 140 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 141         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
 142         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
 143         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
 144         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
 145         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
 146         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
 147         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
 148         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
 149         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
 150         .grp_ddrmode_ctl = 0x00020000,
 151         .grp_ddrpke = 0x00000000,
 152         .grp_ddrmode = 0x00020000,
 153         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
 154         .grp_ddr_type = 0x000c0000,
 155 };
 156
 157 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 158 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 159         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
 160         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
 161         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
 162         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
 163         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
 164         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
 165         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 166         .dram_sdba2 = 0x00000000,
 167         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 168         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 169         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 170         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 171         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 172         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 173         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 174         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 175         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 176         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 177         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 178         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 179         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 180         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 181         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 182         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 183         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 184         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 185 };
 186
 187 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 188 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 189         .grp_ddr_type = 0x000c0000,
 190         .grp_ddrmode_ctl = 0x00020000,
 191         .grp_ddrpke = 0x00000000,
 192         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 193         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 194         .grp_ddrmode = 0x00020000,
 195         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 196         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 197         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 198         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 199         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 200         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 201         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 202         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 203 };
 204
 205 /* mt41j256 */
 206 static struct mx6_ddr3_cfg mt41j256 = {
 207         .mem_speed = 1066,
 208         .density = 2,
 209         .width = 16,
 210         .banks = 8,
 211         .rowaddr = 13,
 212         .coladdr = 10,
 213         .pagesz = 2,
 214         .trcd = 1375,
 215         .trcmin = 4875,
 216         .trasmin = 3500,
 217         .SRT = 0,
 218 };
 219
 220 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 221         .p0_mpwldectrl0 = 0x000E0009,
 222         .p0_mpwldectrl1 = 0x0018000E,
 223         .p1_mpwldectrl0 = 0x00000007,
 224         .p1_mpwldectrl1 = 0x00000000,
 225         .p0_mpdgctrl0 = 0x43280334,
 226         .p0_mpdgctrl1 = 0x031C0314,
 227         .p1_mpdgctrl0 = 0x4318031C,
 228         .p1_mpdgctrl1 = 0x030C0258,
 229         .p0_mprddlctl = 0x3E343A40,
 230         .p1_mprddlctl = 0x383C3844,
 231         .p0_mpwrdlctl = 0x40404440,
 232         .p1_mpwrdlctl = 0x4C3E4446,
 233 };
 234
 235 /* DDR 64bit */
 236 static struct mx6_ddr_sysinfo mem_q = {
 237         .ddr_type       = DDR_TYPE_DDR3,
 238         .dsize          = 2,
 239         .cs1_mirror     = 0,
 240         /* config for full 4GB range so that get_mem_size() works */
 241         .cs_density     = 32,
 242         .ncs            = 1,
 243         .bi_on          = 1,
 244         .rtt_nom        = 2,
 245         .rtt_wr         = 2,
 246         .ralat          = 5,
 247         .walat          = 0,
 248         .mif3_mode      = 3,
 249         .rst_to_cke     = 0x23,
 250         .sde_to_rst     = 0x10,
 251 };
 252
 253 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 254         .p0_mpwldectrl0 = 0x001F0024,
 255         .p0_mpwldectrl1 = 0x00110018,
 256         .p1_mpwldectrl0 = 0x001F0024,
 257         .p1_mpwldectrl1 = 0x00110018,
 258         .p0_mpdgctrl0 = 0x4230022C,
 259         .p0_mpdgctrl1 = 0x02180220,
 260         .p1_mpdgctrl0 = 0x42440248,
 261         .p1_mpdgctrl1 = 0x02300238,
 262         .p0_mprddlctl = 0x44444A48,
 263         .p1_mprddlctl = 0x46484A42,
 264         .p0_mpwrdlctl = 0x38383234,
 265         .p1_mpwrdlctl = 0x3C34362E,
 266 };
 267
 268 /* DDR 64bit 1GB */
 269 static struct mx6_ddr_sysinfo mem_dl = {
 270         .dsize          = 2,
 271         .cs1_mirror     = 0,
 272         /* config for full 4GB range so that get_mem_size() works */
 273         .cs_density     = 32,
 274         .ncs            = 1,
 275         .bi_on          = 1,
 276         .rtt_nom        = 1,
 277         .rtt_wr         = 1,
 278         .ralat          = 5,
 279         .walat          = 0,
 280         .mif3_mode      = 3,
 281         .rst_to_cke     = 0x23,
 282         .sde_to_rst     = 0x10,
 283 };
 284
 285 /* DDR 32bit 512MB */
 286 static struct mx6_ddr_sysinfo mem_s = {
 287         .dsize          = 1,
 288         .cs1_mirror     = 0,
 289         /* config for full 4GB range so that get_mem_size() works */
 290         .cs_density     = 32,
 291         .ncs            = 1,
 292         .bi_on          = 1,
 293         .rtt_nom        = 1,
 294         .rtt_wr         = 1,
 295         .ralat          = 5,
 296         .walat          = 0,
 297         .mif3_mode      = 3,
 298         .rst_to_cke     = 0x23,
 299         .sde_to_rst     = 0x10,
 300 };
 301 #endif /* CONFIG_MX6QDL */
 302
 303 #ifdef CONFIG_MX6UL
 304 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 305         .grp_addds = 0x00000030,
 306         .grp_ddrmode_ctl = 0x00020000,
 307         .grp_b0ds = 0x00000030,
 308         .grp_ctlds = 0x00000030,
 309         .grp_b1ds = 0x00000030,
 310         .grp_ddrpke = 0x00000000,
 311         .grp_ddrmode = 0x00020000,
 312         .grp_ddr_type = 0x000c0000,
 313 };
 314
 315 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 316         .dram_dqm0 = 0x00000030,
 317         .dram_dqm1 = 0x00000030,
 318         .dram_ras = 0x00000030,
 319         .dram_cas = 0x00000030,
 320         .dram_odt0 = 0x00000030,
 321         .dram_odt1 = 0x00000030,
 322         .dram_sdba2 = 0x00000000,
 323         .dram_sdclk_0 = 0x00000008,
 324         .dram_sdqs0 = 0x00000038,
 325         .dram_sdqs1 = 0x00000030,
 326         .dram_reset = 0x00000030,
 327 };
 328
 329 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 330         .p0_mpwldectrl0 = 0x00070007,
 331         .p0_mpdgctrl0 = 0x41490145,
 332         .p0_mprddlctl = 0x40404546,
 333         .p0_mpwrdlctl = 0x4040524D,
 334 };
 335
 336 struct mx6_ddr_sysinfo ddr_sysinfo = {
 337         .dsize = 0,
 338         .cs_density = 20,
 339         .ncs = 1,
 340         .cs1_mirror = 0,
 341         .rtt_wr = 2,
 342         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 343         .walat = 1,             /* Write additional latency */
 344         .ralat = 5,             /* Read additional latency */
 345         .mif3_mode = 3,         /* Command prediction working mode */
 346         .bi_on = 1,             /* Bank interleaving enabled */
 347         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 348         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 349         .ddr_type = DDR_TYPE_DDR3,
 350 };
 351
 352 static struct mx6_ddr3_cfg mem_ddr = {
 353         .mem_speed = 800,
 354         .density = 4,
 355         .width = 16,
 356         .banks = 8,
 357 #ifdef TARGET_MX6UL_ISIOT
 358         .rowaddr = 15,
 359 #else
 360         .rowaddr = 13,
 361 #endif
 362         .coladdr = 10,
 363         .pagesz = 2,
 364         .trcd = 1375,
 365         .trcmin = 4875,
 366         .trasmin = 3500,
 367 };
 368 #endif /* CONFIG_MX6UL */
 369
 370 static void ccgr_init(void)
 371 {
 372         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 373
 374 #ifdef CONFIG_MX6QDL
 375         writel(0x00003F3F, &ccm->CCGR0);
 376         writel(0x0030FC00, &ccm->CCGR1);
 377         writel(0x000FC000, &ccm->CCGR2);
 378         writel(0x3F300000, &ccm->CCGR3);
 379         writel(0xFF00F300, &ccm->CCGR4);
 380         writel(0x0F0000C3, &ccm->CCGR5);
 381         writel(0x000003CC, &ccm->CCGR6);
 382 #elif CONFIG_MX6UL
 383         writel(0x00c03f3f, &ccm->CCGR0);
 384         writel(0xfcffff00, &ccm->CCGR1);
 385         writel(0x0cffffcc, &ccm->CCGR2);
 386         writel(0x3f3c3030, &ccm->CCGR3);
 387         writel(0xff00fffc, &ccm->CCGR4);
 388         writel(0x033f30ff, &ccm->CCGR5);
 389         writel(0x00c00fff, &ccm->CCGR6);
 390 #endif
 391 }
 392
 393 static void spl_dram_init(void)
 394 {
 395 #ifdef CONFIG_MX6QDL
 396         if (is_mx6solo()) {
 397                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 398                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 399         } else if (is_mx6dl()) {
 400                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 401                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 402         } else if (is_mx6dq()) {
 403                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 404                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 405         }
 406 #elif CONFIG_MX6UL
 407         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 408         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 409 #endif
 410
 411         udelay(100);
 412 }
 413
 414 void board_init_f(ulong dummy)
 415 {
 416         ccgr_init();
 417
 418         /* setup AIPS and disable watchdog */
 419         arch_cpu_init();
 420
 421         if (!(is_mx6ul()))
 422                 gpr_init();
 423
 424         /* iomux */
 425         SETUP_IOMUX_PADS(uart_pads);
 426
 427         /* setup GP timer */
 428         timer_init();
 429
 430         /* UART clocks enabled and gd valid - init serial console */
 431         preloader_console_init();
 432
 433         /* DDR initialization */
 434         spl_dram_init();
 435 }