board/engicam/common/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Amarula Solutions B.V.
   4  * Copyright (C) 2016 Engicam S.r.l.
   5  * Author: Jagan Teki <jagan@amarulasolutions.com>
   6  */
   7
   8 #include <common.h>
   9 #include <image.h>
  10 #include <init.h>
  11 #include <serial.h>
  12 #include <spl.h>
  13
  14 #include <asm/io.h>
  15 #include <asm/gpio.h>
  16 #include <linux/sizes.h>
  17
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/arch/iomux.h>
  21 #include <asm/arch/mx6-ddr.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/sys_proto.h>
  24
  25 #include <asm/mach-imx/iomux-v3.h>
  26 #include <asm/mach-imx/video.h>
  27
  28 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  29         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  30         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  31
  32 static iomux_v3_cfg_t const uart_pads[] = {
  33 #ifdef CONFIG_MX6QDL
  34         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  35         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  36 #elif CONFIG_MX6UL
  37         IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
  38         IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
  39 #endif
  40 };
  41
  42 #ifdef CONFIG_SPL_LOAD_FIT
  43 int board_fit_config_name_match(const char *name)
  44 {
  45         if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
  46                 return 0;
  47         else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
  48                 return 0;
  49         else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi"))
  50                 return 0;
  51         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
  52                 return 0;
  53         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
  54                 return 0;
  55         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi"))
  56                 return 0;
  57         else
  58                 return -1;
  59 }
  60 #endif
  61
  62 #ifdef CONFIG_ENV_IS_IN_MMC
  63 void board_boot_order(u32 *spl_boot_list)
  64 {
  65         u32 bmode = imx6_src_get_boot_mode();
  66         u8 boot_dev = BOOT_DEVICE_MMC1;
  67
  68         switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
  69         case IMX6_BMODE_SD:
  70         case IMX6_BMODE_ESD:
  71                 /* SD/eSD - BOOT_DEVICE_MMC1 */
  72                 break;
  73         case IMX6_BMODE_MMC:
  74         case IMX6_BMODE_EMMC:
  75                 /* MMC/eMMC */
  76                 boot_dev = BOOT_DEVICE_MMC2;
  77                 break;
  78         default:
  79                 /* Default - BOOT_DEVICE_MMC1 */
  80                 printf("Wrong board boot order\n");
  81                 break;
  82         }
  83
  84         spl_boot_list[0] = boot_dev;
  85 }
  86 #endif
  87
  88 #ifdef CONFIG_SPL_OS_BOOT
  89 int spl_start_uboot(void)
  90 {
  91         /* break into full u-boot on 'c' */
  92         if (serial_tstc() && serial_getc() == 'c')
  93                 return 1;
  94
  95         return 0;
  96 }
  97 #endif
  98
  99 #ifdef CONFIG_MX6QDL
 100 /*
 101  * Driving strength:
 102  *   0x30 == 40 Ohm
 103  *   0x28 == 48 Ohm
 104  */
 105 #define IMX6DQ_DRIVE_STRENGTH           0x30
 106 #define IMX6SDL_DRIVE_STRENGTH          0x28
 107
 108 /* configure MX6Q/DUAL mmdc DDR io registers */
 109 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 110         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
 111         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
 112         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
 113         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
 114         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
 115         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
 116         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
 117         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
 118         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
 119         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
 120         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
 121         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
 122         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
 123         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
 124         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
 125         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
 126         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
 127         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
 128         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
 129         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
 130         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
 131         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
 132         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
 133         .dram_sdba2 = 0x00000000,
 134         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
 135         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
 136 };
 137
 138 /* configure MX6Q/DUAL mmdc GRP io registers */
 139 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 140         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
 141         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
 142         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
 143         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
 144         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
 145         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
 146         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
 147         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
 148         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
 149         .grp_ddrmode_ctl = 0x00020000,
 150         .grp_ddrpke = 0x00000000,
 151         .grp_ddrmode = 0x00020000,
 152         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
 153         .grp_ddr_type = 0x000c0000,
 154 };
 155
 156 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 157 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 158         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
 159         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
 160         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
 161         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
 162         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
 163         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
 164         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 165         .dram_sdba2 = 0x00000000,
 166         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 167         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 168         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 169         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 170         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 171         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 172         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 173         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 174         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 175         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 176         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 177         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 178         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 179         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 180         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 181         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 182         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 183         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 184 };
 185
 186 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 187 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 188         .grp_ddr_type = 0x000c0000,
 189         .grp_ddrmode_ctl = 0x00020000,
 190         .grp_ddrpke = 0x00000000,
 191         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 192         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 193         .grp_ddrmode = 0x00020000,
 194         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 195         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 196         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 197         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 198         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 199         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 200         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 201         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 202 };
 203
 204 /* mt41j256 */
 205 static struct mx6_ddr3_cfg mt41j256 = {
 206         .mem_speed = 1066,
 207         .density = 2,
 208         .width = 16,
 209         .banks = 8,
 210         .rowaddr = 13,
 211         .coladdr = 10,
 212         .pagesz = 2,
 213         .trcd = 1375,
 214         .trcmin = 4875,
 215         .trasmin = 3500,
 216         .SRT = 0,
 217 };
 218
 219 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 220         .p0_mpwldectrl0 = 0x000E0009,
 221         .p0_mpwldectrl1 = 0x0018000E,
 222         .p1_mpwldectrl0 = 0x00000007,
 223         .p1_mpwldectrl1 = 0x00000000,
 224         .p0_mpdgctrl0 = 0x43280334,
 225         .p0_mpdgctrl1 = 0x031C0314,
 226         .p1_mpdgctrl0 = 0x4318031C,
 227         .p1_mpdgctrl1 = 0x030C0258,
 228         .p0_mprddlctl = 0x3E343A40,
 229         .p1_mprddlctl = 0x383C3844,
 230         .p0_mpwrdlctl = 0x40404440,
 231         .p1_mpwrdlctl = 0x4C3E4446,
 232 };
 233
 234 /* DDR 64bit */
 235 static struct mx6_ddr_sysinfo mem_q = {
 236         .ddr_type       = DDR_TYPE_DDR3,
 237         .dsize          = 2,
 238         .cs1_mirror     = 0,
 239         /* config for full 4GB range so that get_mem_size() works */
 240         .cs_density     = 32,
 241         .ncs            = 1,
 242         .bi_on          = 1,
 243         .rtt_nom        = 2,
 244         .rtt_wr         = 2,
 245         .ralat          = 5,
 246         .walat          = 0,
 247         .mif3_mode      = 3,
 248         .rst_to_cke     = 0x23,
 249         .sde_to_rst     = 0x10,
 250 };
 251
 252 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 253         .p0_mpwldectrl0 = 0x001F0024,
 254         .p0_mpwldectrl1 = 0x00110018,
 255         .p1_mpwldectrl0 = 0x001F0024,
 256         .p1_mpwldectrl1 = 0x00110018,
 257         .p0_mpdgctrl0 = 0x4230022C,
 258         .p0_mpdgctrl1 = 0x02180220,
 259         .p1_mpdgctrl0 = 0x42440248,
 260         .p1_mpdgctrl1 = 0x02300238,
 261         .p0_mprddlctl = 0x44444A48,
 262         .p1_mprddlctl = 0x46484A42,
 263         .p0_mpwrdlctl = 0x38383234,
 264         .p1_mpwrdlctl = 0x3C34362E,
 265 };
 266
 267 /* DDR 64bit 1GB */
 268 static struct mx6_ddr_sysinfo mem_dl = {
 269         .dsize          = 2,
 270         .cs1_mirror     = 0,
 271         /* config for full 4GB range so that get_mem_size() works */
 272         .cs_density     = 32,
 273         .ncs            = 1,
 274         .bi_on          = 1,
 275         .rtt_nom        = 1,
 276         .rtt_wr         = 1,
 277         .ralat          = 5,
 278         .walat          = 0,
 279         .mif3_mode      = 3,
 280         .rst_to_cke     = 0x23,
 281         .sde_to_rst     = 0x10,
 282 };
 283
 284 /* DDR 32bit 512MB */
 285 static struct mx6_ddr_sysinfo mem_s = {
 286         .dsize          = 1,
 287         .cs1_mirror     = 0,
 288         /* config for full 4GB range so that get_mem_size() works */
 289         .cs_density     = 32,
 290         .ncs            = 1,
 291         .bi_on          = 1,
 292         .rtt_nom        = 1,
 293         .rtt_wr         = 1,
 294         .ralat          = 5,
 295         .walat          = 0,
 296         .mif3_mode      = 3,
 297         .rst_to_cke     = 0x23,
 298         .sde_to_rst     = 0x10,
 299 };
 300 #endif /* CONFIG_MX6QDL */
 301
 302 #ifdef CONFIG_MX6UL
 303 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 304         .grp_addds = 0x00000030,
 305         .grp_ddrmode_ctl = 0x00020000,
 306         .grp_b0ds = 0x00000030,
 307         .grp_ctlds = 0x00000030,
 308         .grp_b1ds = 0x00000030,
 309         .grp_ddrpke = 0x00000000,
 310         .grp_ddrmode = 0x00020000,
 311         .grp_ddr_type = 0x000c0000,
 312 };
 313
 314 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 315         .dram_dqm0 = 0x00000030,
 316         .dram_dqm1 = 0x00000030,
 317         .dram_ras = 0x00000030,
 318         .dram_cas = 0x00000030,
 319         .dram_odt0 = 0x00000030,
 320         .dram_odt1 = 0x00000030,
 321         .dram_sdba2 = 0x00000000,
 322         .dram_sdclk_0 = 0x00000008,
 323         .dram_sdqs0 = 0x00000038,
 324         .dram_sdqs1 = 0x00000030,
 325         .dram_reset = 0x00000030,
 326 };
 327
 328 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 329         .p0_mpwldectrl0 = 0x00070007,
 330         .p0_mpdgctrl0 = 0x41490145,
 331         .p0_mprddlctl = 0x40404546,
 332         .p0_mpwrdlctl = 0x4040524D,
 333 };
 334
 335 struct mx6_ddr_sysinfo ddr_sysinfo = {
 336         .dsize = 0,
 337         .cs_density = 20,
 338         .ncs = 1,
 339         .cs1_mirror = 0,
 340         .rtt_wr = 2,
 341         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 342         .walat = 1,             /* Write additional latency */
 343         .ralat = 5,             /* Read additional latency */
 344         .mif3_mode = 3,         /* Command prediction working mode */
 345         .bi_on = 1,             /* Bank interleaving enabled */
 346         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 347         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 348         .ddr_type = DDR_TYPE_DDR3,
 349 };
 350
 351 static struct mx6_ddr3_cfg mem_ddr = {
 352         .mem_speed = 800,
 353         .density = 4,
 354         .width = 16,
 355         .banks = 8,
 356 #ifdef TARGET_MX6UL_ISIOT
 357         .rowaddr = 15,
 358 #else
 359         .rowaddr = 13,
 360 #endif
 361         .coladdr = 10,
 362         .pagesz = 2,
 363         .trcd = 1375,
 364         .trcmin = 4875,
 365         .trasmin = 3500,
 366 };
 367 #endif /* CONFIG_MX6UL */
 368
 369 static void ccgr_init(void)
 370 {
 371         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 372
 373 #ifdef CONFIG_MX6QDL
 374         writel(0x00003F3F, &ccm->CCGR0);
 375         writel(0x0030FC00, &ccm->CCGR1);
 376         writel(0x000FC000, &ccm->CCGR2);
 377         writel(0x3F300000, &ccm->CCGR3);
 378         writel(0xFF00F300, &ccm->CCGR4);
 379         writel(0x0F0000C3, &ccm->CCGR5);
 380         writel(0x000003CC, &ccm->CCGR6);
 381 #elif CONFIG_MX6UL
 382         writel(0x00c03f3f, &ccm->CCGR0);
 383         writel(0xfcffff00, &ccm->CCGR1);
 384         writel(0x0cffffcc, &ccm->CCGR2);
 385         writel(0x3f3c3030, &ccm->CCGR3);
 386         writel(0xff00fffc, &ccm->CCGR4);
 387         writel(0x033f30ff, &ccm->CCGR5);
 388         writel(0x00c00fff, &ccm->CCGR6);
 389 #endif
 390 }
 391
 392 static void spl_dram_init(void)
 393 {
 394 #ifdef CONFIG_MX6QDL
 395         if (is_mx6solo()) {
 396                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 397                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 398         } else if (is_mx6dl()) {
 399                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 400                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 401         } else if (is_mx6dq()) {
 402                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 403                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 404         }
 405 #elif CONFIG_MX6UL
 406         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 407         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 408 #endif
 409
 410         udelay(100);
 411 }
 412
 413 void board_init_f(ulong dummy)
 414 {
 415         ccgr_init();
 416
 417         /* setup AIPS and disable watchdog */
 418         arch_cpu_init();
 419
 420         if (!(is_mx6ul()))
 421                 gpr_init();
 422
 423         /* iomux */
 424         SETUP_IOMUX_PADS(uart_pads);
 425
 426         /* setup GP timer */
 427         timer_init();
 428
 429         /* UART clocks enabled and gd valid - init serial console */
 430         preloader_console_init();
 431
 432         /* DDR initialization */
 433         spl_dram_init();
 434 }