board/embest/mx6boards/mx6boards.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Eukréa Electromatique
   4  * Author: Eric Bénard <eric@eukrea.com>
   5  *         Fabio Estevam <fabio.estevam@freescale.com>
   6  *         Jon Nettleton <jon.nettleton@gmail.com>
   7  *
   8  * based on sabresd.c which is :
   9  * Copyright (C) 2012 Freescale Semiconductor, Inc.
  10  * and on hummingboard.c which is :
  11  * Copyright (C) 2013 SolidRun ltd.
  12  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
  13  */
  14
  15 #include <common.h>
  16 #include <init.h>
  17 #include <net.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include <asm/arch/iomux.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <linux/errno.h>
  24 #include <asm/gpio.h>
  25 #include <asm/mach-imx/iomux-v3.h>
  26 #include <asm/mach-imx/boot_mode.h>
  27 #include <asm/mach-imx/mxc_i2c.h>
  28 #include <asm/mach-imx/spi.h>
  29 #include <asm/mach-imx/video.h>
  30 #include <i2c.h>
  31 #include <input.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc_imx.h>
  34 #include <miiphy.h>
  35 #include <netdev.h>
  36 #include <asm/arch/mxc_hdmi.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <linux/fb.h>
  39 #include <ipu_pixfmt.h>
  40 #include <asm/io.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  49         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW |         \
  53         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST |                  \
  54         PAD_CTL_HYS)
  55
  56 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58
  59 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  61
  62 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  63         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  64
  65 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  66         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  67         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  68
  69 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  70                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  71
  72 static int board_type = -1;
  73 #define BOARD_IS_MARSBOARD      0
  74 #define BOARD_IS_RIOTBOARD      1
  75
  76 int dram_init(void)
  77 {
  78         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  79
  80         return 0;
  81 }
  82
  83 static iomux_v3_cfg_t const uart2_pads[] = {
  84         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86 };
  87
  88 static void setup_iomux_uart(void)
  89 {
  90         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  91 }
  92
  93 iomux_v3_cfg_t const enet_pads[] = {
  94         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         /* GPIO16 -> AR8035 25MHz */
  97         MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  98         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
  99         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 101         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 102         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 103         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 104         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 105         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
 106         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 107         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 108         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 109         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 110         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 111         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 112         /* AR8035 PHY Reset */
 113         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 114         /* AR8035 PHY Interrupt */
 115         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116 };
 117
 118 static void setup_iomux_enet(void)
 119 {
 120         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 121
 122         /* Reset AR8035 PHY */
 123         gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
 124         mdelay(2);
 125         gpio_set_value(IMX_GPIO_NR(3, 31), 1);
 126 }
 127
 128 int mx6_rgmii_rework(struct phy_device *phydev)
 129 {
 130         /* from linux/arch/arm/mach-imx/mach-imx6q.c :
 131          * Ar803x phy SmartEEE feature cause link status generates glitch,
 132          * which cause ethernet link down/up issue, so disable SmartEEE
 133          */
 134         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 135         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 136         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 137
 138         return 0;
 139 }
 140
 141 int board_phy_config(struct phy_device *phydev)
 142 {
 143         mx6_rgmii_rework(phydev);
 144
 145         if (phydev->drv->config)
 146                 phydev->drv->config(phydev);
 147
 148         return 0;
 149 }
 150
 151 iomux_v3_cfg_t const usdhc2_pads[] = {
 152         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
 153         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 158         MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
 159         MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 160 };
 161
 162 iomux_v3_cfg_t const usdhc3_pads[] = {
 163         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
 164         MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169 };
 170
 171 iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
 172         MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
 173         MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 174 };
 175
 176 iomux_v3_cfg_t const usdhc4_pads[] = {
 177         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
 178         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 179         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 180         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 181         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 182         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 183         /* eMMC RST */
 184         MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 185 };
 186
 187 #ifdef CONFIG_FSL_ESDHC_IMX
 188 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 189         {USDHC2_BASE_ADDR},
 190         {USDHC3_BASE_ADDR},
 191         {USDHC4_BASE_ADDR},
 192 };
 193
 194 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 195 #define USDHC3_CD_GPIO  IMX_GPIO_NR(7, 0)
 196
 197 int board_mmc_getcd(struct mmc *mmc)
 198 {
 199         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 200         int ret = 0;
 201
 202         switch (cfg->esdhc_base) {
 203         case USDHC2_BASE_ADDR:
 204                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 205                 break;
 206         case USDHC3_BASE_ADDR:
 207                 if (board_type == BOARD_IS_RIOTBOARD)
 208                         ret = !gpio_get_value(USDHC3_CD_GPIO);
 209                 else if (board_type == BOARD_IS_MARSBOARD)
 210                         ret = 1; /* eMMC/uSDHC3 is always present */
 211                 break;
 212         case USDHC4_BASE_ADDR:
 213                 ret = 1; /* eMMC/uSDHC4 is always present */
 214                 break;
 215         }
 216
 217         return ret;
 218 }
 219
 220 int board_mmc_init(bd_t *bis)
 221 {
 222         int ret;
 223         int i;
 224
 225         /*
 226          * According to the board_mmc_init() the following map is done:
 227          * (U-Boot device node)    (Physical Port)
 228          * ** RiOTboard :
 229          * mmc0                    SDCard slot (bottom)
 230          * mmc1                    uSDCard slot (top)
 231          * mmc2                    eMMC
 232          * ** MarSBoard :
 233          * mmc0                    uSDCard slot (bottom)
 234          * mmc1                    eMMC
 235          */
 236         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 237                 switch (i) {
 238                 case 0:
 239                         imx_iomux_v3_setup_multiple_pads(
 240                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 241                         gpio_direction_input(USDHC2_CD_GPIO);
 242                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 243                         usdhc_cfg[0].max_bus_width = 4;
 244                         break;
 245                 case 1:
 246                         imx_iomux_v3_setup_multiple_pads(
 247                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 248                         if (board_type == BOARD_IS_RIOTBOARD) {
 249                                 imx_iomux_v3_setup_multiple_pads(
 250                                         riotboard_usdhc3_pads,
 251                                         ARRAY_SIZE(riotboard_usdhc3_pads));
 252                                 gpio_direction_input(USDHC3_CD_GPIO);
 253                         } else {
 254                                 gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
 255                                 udelay(250);
 256                                 gpio_set_value(IMX_GPIO_NR(7, 8), 1);
 257                         }
 258                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 259                         usdhc_cfg[1].max_bus_width = 4;
 260                         break;
 261                 case 2:
 262                         imx_iomux_v3_setup_multiple_pads(
 263                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 264                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 265                         usdhc_cfg[2].max_bus_width = 4;
 266                         gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
 267                         udelay(250);
 268                         gpio_set_value(IMX_GPIO_NR(6, 8), 1);
 269                         break;
 270                 default:
 271                         printf("Warning: you configured more USDHC controllers"
 272                                "(%d) then supported by the board (%d)\n",
 273                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 274                         return -EINVAL;
 275                 }
 276
 277                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 278                 if (ret)
 279                         return ret;
 280         }
 281
 282         return 0;
 283 }
 284 #endif
 285
 286 #ifdef CONFIG_MXC_SPI
 287 iomux_v3_cfg_t const ecspi1_pads[] = {
 288         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 289         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 290         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 291         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 292 };
 293
 294 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 295 {
 296         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 297 }
 298
 299 static void setup_spi(void)
 300 {
 301         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 302 }
 303 #endif
 304
 305 struct i2c_pads_info i2c_pad_info1 = {
 306         .scl = {
 307                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
 308                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 309                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
 310                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 311                 .gp = IMX_GPIO_NR(5, 27)
 312         },
 313         .sda = {
 314                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
 315                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 316                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
 317                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 318                 .gp = IMX_GPIO_NR(5, 26)
 319         }
 320 };
 321
 322 struct i2c_pads_info i2c_pad_info2 = {
 323         .scl = {
 324                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
 325                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 326                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
 327                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 328                 .gp = IMX_GPIO_NR(4, 12)
 329         },
 330         .sda = {
 331                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
 332                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 333                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
 334                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 335                 .gp = IMX_GPIO_NR(4, 13)
 336         }
 337 };
 338
 339 struct i2c_pads_info i2c_pad_info3 = {
 340         .scl = {
 341                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
 342                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 343                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
 344                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 345                 .gp = IMX_GPIO_NR(1, 5)
 346         },
 347         .sda = {
 348                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
 349                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 350                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
 351                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 352                 .gp = IMX_GPIO_NR(1, 6)
 353         }
 354 };
 355
 356 iomux_v3_cfg_t const tft_pads_riot[] = {
 357         /* LCD_PWR_EN */
 358         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 359         /* TOUCH_INT */
 360         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 361         /* LED_PWR_EN */
 362         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 363         /* BL LEVEL */
 364         MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 365 };
 366
 367 iomux_v3_cfg_t const tft_pads_mars[] = {
 368         /* LCD_PWR_EN */
 369         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 370         /* TOUCH_INT */
 371         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 372         /* LED_PWR_EN */
 373         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 374         /* BL LEVEL (PWM4) */
 375         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 376 };
 377
 378 #if defined(CONFIG_VIDEO_IPUV3)
 379
 380 static void enable_lvds(struct display_info_t const *dev)
 381 {
 382         struct iomuxc *iomux = (struct iomuxc *)
 383                                 IOMUXC_BASE_ADDR;
 384         setbits_le32(&iomux->gpr[2],
 385                      IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
 386         /* set backlight level to ON */
 387         if (board_type == BOARD_IS_RIOTBOARD)
 388                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
 389         else if (board_type == BOARD_IS_MARSBOARD)
 390                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
 391 }
 392
 393 static void disable_lvds(struct display_info_t const *dev)
 394 {
 395         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 396
 397         /* set backlight level to OFF */
 398         if (board_type == BOARD_IS_RIOTBOARD)
 399                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
 400         else if (board_type == BOARD_IS_MARSBOARD)
 401                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
 402
 403         clrbits_le32(&iomux->gpr[2],
 404                      IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
 405 }
 406
 407 static void do_enable_hdmi(struct display_info_t const *dev)
 408 {
 409         disable_lvds(dev);
 410         imx_enable_hdmi_phy();
 411 }
 412
 413 static int detect_i2c(struct display_info_t const *dev)
 414 {
 415         return (0 == i2c_set_bus_num(dev->bus)) &&
 416                 (0 == i2c_probe(dev->addr));
 417 }
 418
 419 struct display_info_t const displays[] = {{
 420         .bus    = -1,
 421         .addr   = 0,
 422         .pixfmt = IPU_PIX_FMT_RGB24,
 423         .detect = detect_hdmi,
 424         .enable = do_enable_hdmi,
 425         .mode   = {
 426                 .name           = "HDMI",
 427                 .refresh        = 60,
 428                 .xres           = 1024,
 429                 .yres           = 768,
 430                 .pixclock       = 15385,
 431                 .left_margin    = 220,
 432                 .right_margin   = 40,
 433                 .upper_margin   = 21,
 434                 .lower_margin   = 7,
 435                 .hsync_len      = 60,
 436                 .vsync_len      = 10,
 437                 .sync           = FB_SYNC_EXT,
 438                 .vmode          = FB_VMODE_NONINTERLACED
 439 } }, {
 440         .bus    = 2,
 441         .addr   = 0x1,
 442         .pixfmt = IPU_PIX_FMT_LVDS666,
 443         .detect = detect_i2c,
 444         .enable = enable_lvds,
 445         .mode   = {
 446                 .name           = "LCD8000-97C",
 447                 .refresh        = 60,
 448                 .xres           = 1024,
 449                 .yres           = 768,
 450                 .pixclock       = 15385,
 451                 .left_margin    = 100,
 452                 .right_margin   = 200,
 453                 .upper_margin   = 10,
 454                 .lower_margin   = 20,
 455                 .hsync_len      = 20,
 456                 .vsync_len      = 8,
 457                 .sync           = FB_SYNC_EXT,
 458                 .vmode          = FB_VMODE_NONINTERLACED
 459 } } };
 460 size_t display_count = ARRAY_SIZE(displays);
 461
 462 static void setup_display(void)
 463 {
 464         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 465         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 466         int reg;
 467
 468         enable_ipu_clock();
 469         imx_setup_hdmi();
 470
 471         /* Turn on LDB0, IPU,IPU DI0 clocks */
 472         setbits_le32(&mxc_ccm->CCGR3,
 473                      MXC_CCM_CCGR3_LDB_DI0_MASK);
 474
 475         /* set LDB0 clk select to 011/011 */
 476         clrsetbits_le32(&mxc_ccm->cs2cdr,
 477                         MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
 478                         (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
 479
 480         setbits_le32(&mxc_ccm->cscmr2,
 481                      MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 482
 483         setbits_le32(&mxc_ccm->chsccdr,
 484                      (CHSCCDR_CLK_SEL_LDB_DI0
 485                      << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 486
 487         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 488              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 489              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 490              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 491              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 492              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 493              | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 494              | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 495         writel(reg, &iomux->gpr[2]);
 496
 497         clrsetbits_le32(&iomux->gpr[3],
 498                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 499                         IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
 500                         IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 501                         << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 502 }
 503 #endif /* CONFIG_VIDEO_IPUV3 */
 504
 505 /*
 506  * Do not overwrite the console
 507  * Use always serial for U-Boot console
 508  */
 509 int overwrite_console(void)
 510 {
 511         return 1;
 512 }
 513
 514 int board_eth_init(bd_t *bis)
 515 {
 516         setup_iomux_enet();
 517
 518         return cpu_eth_init(bis);
 519 }
 520
 521 int board_early_init_f(void)
 522 {
 523         u32 cputype = cpu_type(get_cpu_rev());
 524
 525         switch (cputype) {
 526         case MXC_CPU_MX6SOLO:
 527                 board_type = BOARD_IS_RIOTBOARD;
 528                 break;
 529         case MXC_CPU_MX6D:
 530                 board_type = BOARD_IS_MARSBOARD;
 531                 break;
 532         }
 533
 534         setup_iomux_uart();
 535
 536         if (board_type == BOARD_IS_RIOTBOARD)
 537                 imx_iomux_v3_setup_multiple_pads(
 538                         tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
 539         else if (board_type == BOARD_IS_MARSBOARD)
 540                 imx_iomux_v3_setup_multiple_pads(
 541                         tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
 542 #if defined(CONFIG_VIDEO_IPUV3)
 543         /* power ON LCD */
 544         gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
 545         /* touch interrupt is an input */
 546         gpio_direction_input(IMX_GPIO_NR(6, 14));
 547         /* power ON backlight */
 548         gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
 549         /* set backlight level to off */
 550         if (board_type == BOARD_IS_RIOTBOARD)
 551                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
 552         else if (board_type == BOARD_IS_MARSBOARD)
 553                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
 554         setup_display();
 555 #endif
 556
 557         return 0;
 558 }
 559
 560 int board_init(void)
 561 {
 562         /* address of boot parameters */
 563         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 564         /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
 565         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 566         /* i2c2 : HDMI EDID */
 567         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 568         /* i2c3 : LVDS, Expansion connector */
 569         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 570 #ifdef CONFIG_MXC_SPI
 571         setup_spi();
 572 #endif
 573         return 0;
 574 }
 575
 576 #ifdef CONFIG_CMD_BMODE
 577 static const struct boot_mode riotboard_boot_modes[] = {
 578         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 579         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 580         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 581         {NULL,   0},
 582 };
 583 static const struct boot_mode marsboard_boot_modes[] = {
 584         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 585         {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 586         {NULL,   0},
 587 };
 588 #endif
 589
 590 int board_late_init(void)
 591 {
 592 #ifdef CONFIG_CMD_BMODE
 593         if (board_type == BOARD_IS_RIOTBOARD)
 594                 add_board_boot_modes(riotboard_boot_modes);
 595         else if (board_type == BOARD_IS_RIOTBOARD)
 596                 add_board_boot_modes(marsboard_boot_modes);
 597 #endif
 598
 599         return 0;
 600 }
 601
 602 int checkboard(void)
 603 {
 604         puts("Board: ");
 605         if (board_type == BOARD_IS_MARSBOARD)
 606                 puts("MarSBoard\n");
 607         else if (board_type == BOARD_IS_RIOTBOARD)
 608                 puts("RIoTboard\n");
 609         else
 610                 printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
 611
 612         return 0;
 613 }
 614
 615 #ifdef CONFIG_SPL_BUILD
 616 #include <spl.h>
 617
 618 void board_init_f(ulong dummy)
 619 {
 620         u32 cputype = cpu_type(get_cpu_rev());
 621
 622         switch (cputype) {
 623         case MXC_CPU_MX6SOLO:
 624                 board_type = BOARD_IS_RIOTBOARD;
 625                 break;
 626         case MXC_CPU_MX6D:
 627                 board_type = BOARD_IS_MARSBOARD;
 628                 break;
 629         }
 630         arch_cpu_init();
 631
 632         /* setup GP timer */
 633         timer_init();
 634
 635 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 636         setup_iomux_uart();
 637         preloader_console_init();
 638 #endif
 639 }
 640
 641 void board_boot_order(u32 *spl_boot_list)
 642 {
 643         spl_boot_list[0] = BOOT_DEVICE_MMC1;
 644 }
 645
 646 /*
 647  * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
 648  * to pin 3 (ground).
 649  */
 650 int spl_start_uboot(void)
 651 {
 652         int gpio_key = IMX_GPIO_NR(4, 16);
 653
 654         gpio_direction_input(gpio_key);
 655         if (gpio_get_value(gpio_key) == 0)
 656                 return 1;
 657         else
 658                 return 0;
 659 }
 660
 661 #endif