board/el/el6x/el6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Stefano Babic <sbabic@denx.de>
   4  *
   5  * Based on other i.MX6 boards
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <net.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <env.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <mmc.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <miiphy.h>
  25 #include <netdev.h>
  26 #include <asm/arch/mxc_hdmi.h>
  27 #include <asm/arch/crm_regs.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <i2c.h>
  31 #include <input.h>
  32 #include <power/pmic.h>
  33 #include <power/pfuze100_pmic.h>
  34 #include <asm/arch/mx6-ddr.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define OPEN_PAD_CTRL  (PAD_CTL_ODE  | PAD_CTL_DSE_DISABLE | (0 << 12))
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  45         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  50
  51 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  53
  54 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  55         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  56
  57 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  58         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  59
  60 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  62         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  63
  64 #define I2C_PMIC        1
  65
  66 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  67
  68 #define ETH_PHY_RESET   IMX_GPIO_NR(2, 4)
  69
  70 int dram_init(void)
  71 {
  72         gd->ram_size = imx_ddr_size();
  73
  74         return 0;
  75 }
  76
  77 iomux_v3_cfg_t const uart2_pads[] = {
  78         MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  79         MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80 };
  81
  82 static void setup_iomux_uart(void)
  83 {
  84         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  85 }
  86
  87 #ifdef CONFIG_TARGET_ZC5202
  88 iomux_v3_cfg_t const enet_pads[] = {
  89         MX6_PAD_GPIO_18__ENET_RX_CLK            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_KEY_COL2__ENET_RX_DATA2         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_KEY_COL0__ENET_RX_DATA3         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94         MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
  96         MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_GPIO_19__ENET_TX_ER             | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99         MX6_PAD_KEY_ROW2__ENET_TX_DATA2         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         MX6_PAD_KEY_ROW0__ENET_TX_DATA3         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 101         MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 102         MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 103         /* Switch Reset */
 104         MX6_PAD_NANDF_D4__GPIO2_IO04            | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 105         /* Switch Interrupt */
 106         MX6_PAD_NANDF_D5__GPIO2_IO05            | MUX_PAD_CTRL(NO_PAD_CTRL),
 107         /* use CRS and COL pads as GPIOs */
 108         MX6_PAD_KEY_COL3__GPIO4_IO12            | MUX_PAD_CTRL(OPEN_PAD_CTRL),
 109         MX6_PAD_KEY_ROW1__GPIO4_IO09            | MUX_PAD_CTRL(OPEN_PAD_CTRL),
 110
 111 };
 112
 113 #define BOARD_NAME "EL6x-ZC5202"
 114 #else
 115 iomux_v3_cfg_t const enet_pads[] = {
 116         MX6_PAD_ENET_MDIO__ENET_MDIO    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_ENET_MDC__ENET_MDC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 122         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 123         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 124         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
 125         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 126         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 127         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 128         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 129         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 130         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 131         MX6_PAD_NANDF_D4__GPIO2_IO04            | MUX_PAD_CTRL(NO_PAD_CTRL),
 132         MX6_PAD_NANDF_D5__GPIO2_IO05            | MUX_PAD_CTRL(NO_PAD_CTRL),
 133 };
 134 #define BOARD_NAME "EL6x-ZC5601"
 135 #endif
 136
 137 static void setup_iomux_enet(void)
 138 {
 139         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 140
 141 #ifdef CONFIG_TARGET_ZC5202
 142         /* set CRS and COL to input */
 143         gpio_direction_input(IMX_GPIO_NR(4, 9));
 144         gpio_direction_input(IMX_GPIO_NR(4, 12));
 145
 146         /* Reset Switch */
 147         gpio_direction_output(ETH_PHY_RESET , 0);
 148         mdelay(2);
 149         gpio_set_value(ETH_PHY_RESET, 1);
 150 #endif
 151 }
 152
 153 int board_phy_config(struct phy_device *phydev)
 154 {
 155         if (phydev->drv->config)
 156                 phydev->drv->config(phydev);
 157
 158         return 0;
 159 }
 160
 161 #ifdef CONFIG_MXC_SPI
 162 #ifdef CONFIG_TARGET_ZC5202
 163 iomux_v3_cfg_t const ecspi1_pads[] = {
 164         MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 165         MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 166         MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 167         MX6_PAD_DISP0_DAT23__GPIO5_IO17  | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         MX6_PAD_DISP0_DAT15__GPIO5_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL),
 169 };
 170
 171 iomux_v3_cfg_t const ecspi3_pads[] = {
 172         MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 173         MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 174         MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 175         MX6_PAD_DISP0_DAT7__GPIO4_IO28   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 176         MX6_PAD_DISP0_DAT8__GPIO4_IO29   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 177         MX6_PAD_DISP0_DAT9__GPIO4_IO30   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 178         MX6_PAD_DISP0_DAT10__GPIO4_IO31  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 179 };
 180 #endif
 181
 182 iomux_v3_cfg_t const ecspi4_pads[] = {
 183         MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 184         MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 185         MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 186         MX6_PAD_EIM_D20__GPIO3_IO20  | MUX_PAD_CTRL(NO_PAD_CTRL),
 187 };
 188
 189 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 190 {
 191         return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
 192                 ? (IMX_GPIO_NR(3, 20)) : -1;
 193 }
 194
 195 static void setup_spi(void)
 196 {
 197 #ifdef CONFIG_TARGET_ZC5202
 198         gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
 199         gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
 200         gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
 201         gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
 202         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 203 #endif
 204
 205         gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
 206         gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
 207         imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
 208
 209         enable_spi_clk(true, 3);
 210 }
 211 #endif
 212
 213 static struct i2c_pads_info i2c_pad_info1 = {
 214         .scl = {
 215                 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
 216                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
 217                 .gp = IMX_GPIO_NR(2, 30)
 218         },
 219         .sda = {
 220                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 221                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 222                 .gp = IMX_GPIO_NR(4, 13)
 223         }
 224 };
 225
 226 static struct i2c_pads_info i2c_pad_info2 = {
 227         .scl = {
 228                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
 229                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
 230                 .gp = IMX_GPIO_NR(1, 5)
 231         },
 232         .sda = {
 233                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
 234                 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
 235                 .gp = IMX_GPIO_NR(7, 11)
 236         }
 237 };
 238
 239 iomux_v3_cfg_t const usdhc2_pads[] = {
 240         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 241         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 242         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 243         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 244         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 245         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 246         MX6_PAD_GPIO_4__SD2_CD_B        | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 247 };
 248
 249 iomux_v3_cfg_t const usdhc4_pads[] = {
 250         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 251         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 252         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 253         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 254         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 255         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 256         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 257         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 258         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 259         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 260 };
 261
 262 #ifdef CONFIG_FSL_ESDHC_IMX
 263 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 264         {USDHC2_BASE_ADDR},
 265         {USDHC4_BASE_ADDR},
 266 };
 267
 268 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 269
 270 int board_mmc_getcd(struct mmc *mmc)
 271 {
 272         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 273         int ret = 0;
 274
 275         switch (cfg->esdhc_base) {
 276         case USDHC2_BASE_ADDR:
 277                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 278                 break;
 279         case USDHC4_BASE_ADDR:
 280                 ret = 1; /* eMMC/uSDHC4 is always present */
 281                 break;
 282         }
 283
 284         return ret;
 285 }
 286
 287 int board_mmc_init(bd_t *bis)
 288 {
 289 #ifndef CONFIG_SPL_BUILD
 290         int ret;
 291         int i;
 292
 293         /*
 294          * According to the board_mmc_init() the following map is done:
 295          * (U-boot device node)    (Physical Port)
 296          * mmc0                    SD2
 297          * mmc1                    SD3
 298          * mmc2                    eMMC
 299          */
 300         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 301                 switch (i) {
 302                 case 0:
 303                         imx_iomux_v3_setup_multiple_pads(
 304                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 305                         gpio_direction_input(USDHC2_CD_GPIO);
 306                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 307                         break;
 308                 case 1:
 309                         imx_iomux_v3_setup_multiple_pads(
 310                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 311                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 312                         break;
 313                 default:
 314                         printf("Warning: you configured more USDHC controllers"
 315                                "(%d) then supported by the board (%d)\n",
 316                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 317                         return -EINVAL;
 318                 }
 319
 320                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 321                 if (ret)
 322                         return ret;
 323         }
 324
 325         return 0;
 326 #else
 327         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 328         unsigned reg = readl(&psrc->sbmr1) >> 11;
 329
 330         /*
 331          * Upon reading BOOT_CFG register the following map is done:
 332          * Bit 11 and 12 of BOOT_CFG register can determine the current
 333          * mmc port
 334          * 0x1                  SD1
 335          * 0x2                  SD2
 336          * 0x3                  SD4
 337          */
 338
 339         switch (reg & 0x3) {
 340         case 0x1:
 341                 imx_iomux_v3_setup_multiple_pads(
 342                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 343                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 344                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 345                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 346                 break;
 347         case 0x3:
 348                 imx_iomux_v3_setup_multiple_pads(
 349                         usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 350                 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 351                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 352                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 353                 break;
 354         }
 355
 356         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 357 #endif
 358
 359 }
 360 #endif
 361
 362
 363 /*
 364  * Do not overwrite the console
 365  * Use always serial for U-Boot console
 366  */
 367 int overwrite_console(void)
 368 {
 369         return 1;
 370 }
 371
 372 int board_eth_init(bd_t *bis)
 373 {
 374         setup_iomux_enet();
 375         enable_enet_clk(1);
 376
 377         return cpu_eth_init(bis);
 378 }
 379
 380 int board_early_init_f(void)
 381 {
 382
 383         setup_iomux_uart();
 384         setup_spi();
 385
 386         return 0;
 387 }
 388
 389 int board_init(void)
 390 {
 391         /* address of boot parameters */
 392         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 393
 394         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 395         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 396
 397         return 0;
 398 }
 399
 400 int power_init_board(void)
 401 {
 402         struct pmic *p;
 403         int ret;
 404         unsigned int reg;
 405
 406         ret = power_pfuze100_init(I2C_PMIC);
 407         if (ret)
 408                 return ret;
 409
 410         p = pmic_get("PFUZE100");
 411         ret = pmic_probe(p);
 412         if (ret)
 413                 return ret;
 414
 415         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 416         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 417
 418         /* Increase VGEN3 from 2.5 to 2.8V */
 419         pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 420         reg &= ~LDO_VOL_MASK;
 421         reg |= LDOB_2_80V;
 422         pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
 423
 424         /* Increase VGEN5 from 2.8 to 3V */
 425         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 426         reg &= ~LDO_VOL_MASK;
 427         reg |= LDOB_3_00V;
 428         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 429
 430         /* Set SW1AB stanby volage to 0.975V */
 431         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 432         reg &= ~SW1x_STBY_MASK;
 433         reg |= SW1x_0_975V;
 434         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 435
 436         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 437         pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
 438         reg &= ~SW1xCONF_DVSSPEED_MASK;
 439         reg |= SW1xCONF_DVSSPEED_4US;
 440         pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 441
 442         /* Set SW1C standby voltage to 0.975V */
 443         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 444         reg &= ~SW1x_STBY_MASK;
 445         reg |= SW1x_0_975V;
 446         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 447
 448         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 449         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 450         reg &= ~SW1xCONF_DVSSPEED_MASK;
 451         reg |= SW1xCONF_DVSSPEED_4US;
 452         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 453
 454         return 0;
 455 }
 456
 457 #ifdef CONFIG_CMD_BMODE
 458 static const struct boot_mode board_boot_modes[] = {
 459         /* 4 bit bus width */
 460         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 461         /* 8 bit bus width */
 462         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 463         {NULL,   0},
 464 };
 465 #endif
 466
 467 int board_late_init(void)
 468 {
 469 #ifdef CONFIG_CMD_BMODE
 470         add_board_boot_modes(board_boot_modes);
 471 #endif
 472
 473         env_set("board_name", BOARD_NAME);
 474         return 0;
 475 }
 476
 477 int checkboard(void)
 478 {
 479         puts("Board: ");
 480         puts(BOARD_NAME "\n");
 481
 482         return 0;
 483 }
 484
 485 #ifdef CONFIG_SPL_BUILD
 486 #include <spl.h>
 487 #include <linux/libfdt.h>
 488
 489 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 490         .dram_sdclk_0 =  0x00020030,
 491         .dram_sdclk_1 =  0x00020030,
 492         .dram_cas =  0x00020030,
 493         .dram_ras =  0x00020030,
 494         .dram_reset =  0x00020030,
 495         .dram_sdcke0 =  0x00003000,
 496         .dram_sdcke1 =  0x00003000,
 497         .dram_sdba2 =  0x00000000,
 498         .dram_sdodt0 =  0x00003030,
 499         .dram_sdodt1 =  0x00003030,
 500         .dram_sdqs0 =  0x00000030,
 501         .dram_sdqs1 =  0x00000030,
 502         .dram_sdqs2 =  0x00000030,
 503         .dram_sdqs3 =  0x00000030,
 504         .dram_sdqs4 =  0x00000030,
 505         .dram_sdqs5 =  0x00000030,
 506         .dram_sdqs6 =  0x00000030,
 507         .dram_sdqs7 =  0x00000030,
 508         .dram_dqm0 =  0x00020030,
 509         .dram_dqm1 =  0x00020030,
 510         .dram_dqm2 =  0x00020030,
 511         .dram_dqm3 =  0x00020030,
 512         .dram_dqm4 =  0x00020030,
 513         .dram_dqm5 =  0x00020030,
 514         .dram_dqm6 =  0x00020030,
 515         .dram_dqm7 =  0x00020030,
 516 };
 517
 518 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 519         .grp_ddr_type =  0x000C0000,
 520         .grp_ddrmode_ctl =  0x00020000,
 521         .grp_ddrpke =  0x00000000,
 522         .grp_addds =  0x00000030,
 523         .grp_ctlds =  0x00000030,
 524         .grp_ddrmode =  0x00020000,
 525         .grp_b0ds =  0x00000030,
 526         .grp_b1ds =  0x00000030,
 527         .grp_b2ds =  0x00000030,
 528         .grp_b3ds =  0x00000030,
 529         .grp_b4ds =  0x00000030,
 530         .grp_b5ds =  0x00000030,
 531         .grp_b6ds =  0x00000030,
 532         .grp_b7ds =  0x00000030,
 533 };
 534
 535 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 536         .p0_mpwldectrl0 =  0x001F001F,
 537         .p0_mpwldectrl1 =  0x001F001F,
 538         .p1_mpwldectrl0 =  0x00440044,
 539         .p1_mpwldectrl1 =  0x00440044,
 540         .p0_mpdgctrl0 =  0x434B0350,
 541         .p0_mpdgctrl1 =  0x034C0359,
 542         .p1_mpdgctrl0 =  0x434B0350,
 543         .p1_mpdgctrl1 =  0x03650348,
 544         .p0_mprddlctl =  0x4436383B,
 545         .p1_mprddlctl =  0x39393341,
 546         .p0_mpwrdlctl =  0x35373933,
 547         .p1_mpwrdlctl =  0x48254A36,
 548 };
 549
 550 /* MT41K128M16JT-125 */
 551 static struct mx6_ddr3_cfg mem_ddr = {
 552         .mem_speed = 1600,
 553         .density = 2,
 554         .width = 16,
 555         .banks = 8,
 556         .rowaddr = 14,
 557         .coladdr = 10,
 558         .pagesz = 2,
 559         .trcd = 1375,
 560         .trcmin = 4875,
 561         .trasmin = 3500,
 562 };
 563
 564 static void ccgr_init(void)
 565 {
 566         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 567
 568         writel(0x00C03F3F, &ccm->CCGR0);
 569         writel(0x0030FC03, &ccm->CCGR1);
 570         writel(0x0FFFC000, &ccm->CCGR2);
 571         writel(0x3FF00000, &ccm->CCGR3);
 572         writel(0x00FFF300, &ccm->CCGR4);
 573         writel(0x0F0000C3, &ccm->CCGR5);
 574         writel(0x000003FF, &ccm->CCGR6);
 575 }
 576
 577 /*
 578  * This section requires the differentiation between iMX6 Sabre boards, but
 579  * for now, it will configure only for the mx6q variant.
 580  */
 581 static void spl_dram_init(void)
 582 {
 583         struct mx6_ddr_sysinfo sysinfo = {
 584                 /* width of data bus:0=16,1=32,2=64 */
 585                 .dsize = 2,
 586                 /* config for full 4GB range so that get_mem_size() works */
 587                 .cs_density = 32, /* 32Gb per CS */
 588                 /* single chip select */
 589                 .ncs = 1,
 590                 .cs1_mirror = 0,
 591                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 592                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 593                 .walat = 1,     /* Write additional latency */
 594                 .ralat = 5,     /* Read additional latency */
 595                 .mif3_mode = 3, /* Command prediction working mode */
 596                 .bi_on = 1,     /* Bank interleaving enabled */
 597                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 598                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 599                 .ddr_type = DDR_TYPE_DDR3,
 600                 .refsel = 1,    /* Refresh cycles at 32KHz */
 601                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 602         };
 603
 604         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 605         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 606 }
 607
 608 void board_init_f(ulong dummy)
 609 {
 610         /* setup AIPS and disable watchdog */
 611         arch_cpu_init();
 612
 613         ccgr_init();
 614         gpr_init();
 615
 616         /* iomux and setup of i2c */
 617         board_early_init_f();
 618
 619         /* setup GP timer */
 620         timer_init();
 621
 622         /* UART clocks enabled and gd valid - init serial console */
 623         preloader_console_init();
 624
 625         /* DDR initialization */
 626         spl_dram_init();
 627
 628         /* Clear the BSS. */
 629         memset(__bss_start, 0, __bss_end - __bss_start);
 630
 631         /* load/boot image from boot device */
 632         board_init_r(NULL, 0);
 633 }
 634
 635 #endif