common: Move some board functions out of common.h
[oweals/u-boot.git] / board / el / el6x / el6x.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) Stefano Babic <sbabic@denx.de>
4  *
5  * Based on other i.MX6 boards
6  */
7
8 #include <init.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <env.h>
14 #include <linux/errno.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/video.h>
20 #include <mmc.h>
21 #include <fsl_esdhc_imx.h>
22 #include <miiphy.h>
23 #include <netdev.h>
24 #include <asm/arch/mxc_hdmi.h>
25 #include <asm/arch/crm_regs.h>
26 #include <asm/io.h>
27 #include <asm/arch/sys_proto.h>
28 #include <i2c.h>
29 #include <input.h>
30 #include <power/pmic.h>
31 #include <power/pfuze100_pmic.h>
32 #include <asm/arch/mx6-ddr.h>
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 #define OPEN_PAD_CTRL  (PAD_CTL_ODE  | PAD_CTL_DSE_DISABLE | (0 << 12))
37
38 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
41
42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
43         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
45
46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48
49 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
51
52 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
54
55 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
56         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
57
58 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
60         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
61
62 #define I2C_PMIC        1
63
64 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
65
66 #define ETH_PHY_RESET   IMX_GPIO_NR(2, 4)
67
68 int dram_init(void)
69 {
70         gd->ram_size = imx_ddr_size();
71
72         return 0;
73 }
74
75 iomux_v3_cfg_t const uart2_pads[] = {
76         MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
77         MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78 };
79
80 static void setup_iomux_uart(void)
81 {
82         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
83 }
84
85 #ifdef CONFIG_TARGET_ZC5202
86 iomux_v3_cfg_t const enet_pads[] = {
87         MX6_PAD_GPIO_18__ENET_RX_CLK            | MUX_PAD_CTRL(ENET_PAD_CTRL),
88         MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
89         MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
90         MX6_PAD_KEY_COL2__ENET_RX_DATA2         | MUX_PAD_CTRL(ENET_PAD_CTRL),
91         MX6_PAD_KEY_COL0__ENET_RX_DATA3         | MUX_PAD_CTRL(ENET_PAD_CTRL),
92         MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
93         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
94         MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
95         MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
96         MX6_PAD_GPIO_19__ENET_TX_ER             | MUX_PAD_CTRL(ENET_PAD_CTRL),
97         MX6_PAD_KEY_ROW2__ENET_TX_DATA2         | MUX_PAD_CTRL(ENET_PAD_CTRL),
98         MX6_PAD_KEY_ROW0__ENET_TX_DATA3         | MUX_PAD_CTRL(ENET_PAD_CTRL),
99         MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
100         MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
101         /* Switch Reset */
102         MX6_PAD_NANDF_D4__GPIO2_IO04            | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
103         /* Switch Interrupt */
104         MX6_PAD_NANDF_D5__GPIO2_IO05            | MUX_PAD_CTRL(NO_PAD_CTRL),
105         /* use CRS and COL pads as GPIOs */
106         MX6_PAD_KEY_COL3__GPIO4_IO12            | MUX_PAD_CTRL(OPEN_PAD_CTRL),
107         MX6_PAD_KEY_ROW1__GPIO4_IO09            | MUX_PAD_CTRL(OPEN_PAD_CTRL),
108
109 };
110
111 #define BOARD_NAME "EL6x-ZC5202"
112 #else
113 iomux_v3_cfg_t const enet_pads[] = {
114         MX6_PAD_ENET_MDIO__ENET_MDIO    | MUX_PAD_CTRL(ENET_PAD_CTRL),
115         MX6_PAD_ENET_MDC__ENET_MDC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
116         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
117         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
118         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
119         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
120         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
121         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
122         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
123         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
124         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
125         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
126         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
127         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
128         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
129         MX6_PAD_NANDF_D4__GPIO2_IO04            | MUX_PAD_CTRL(NO_PAD_CTRL),
130         MX6_PAD_NANDF_D5__GPIO2_IO05            | MUX_PAD_CTRL(NO_PAD_CTRL),
131 };
132 #define BOARD_NAME "EL6x-ZC5601"
133 #endif
134
135 static void setup_iomux_enet(void)
136 {
137         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
138
139 #ifdef CONFIG_TARGET_ZC5202
140         /* set CRS and COL to input */
141         gpio_direction_input(IMX_GPIO_NR(4, 9));
142         gpio_direction_input(IMX_GPIO_NR(4, 12));
143
144         /* Reset Switch */
145         gpio_direction_output(ETH_PHY_RESET , 0);
146         mdelay(2);
147         gpio_set_value(ETH_PHY_RESET, 1);
148 #endif
149 }
150
151 int board_phy_config(struct phy_device *phydev)
152 {
153         if (phydev->drv->config)
154                 phydev->drv->config(phydev);
155
156         return 0;
157 }
158
159 #ifdef CONFIG_MXC_SPI
160 #ifdef CONFIG_TARGET_ZC5202
161 iomux_v3_cfg_t const ecspi1_pads[] = {
162         MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
163         MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
164         MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
165         MX6_PAD_DISP0_DAT23__GPIO5_IO17  | MUX_PAD_CTRL(NO_PAD_CTRL),
166         MX6_PAD_DISP0_DAT15__GPIO5_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL),
167 };
168
169 iomux_v3_cfg_t const ecspi3_pads[] = {
170         MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
171         MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
172         MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
173         MX6_PAD_DISP0_DAT7__GPIO4_IO28   | MUX_PAD_CTRL(SPI_PAD_CTRL),
174         MX6_PAD_DISP0_DAT8__GPIO4_IO29   | MUX_PAD_CTRL(SPI_PAD_CTRL),
175         MX6_PAD_DISP0_DAT9__GPIO4_IO30   | MUX_PAD_CTRL(SPI_PAD_CTRL),
176         MX6_PAD_DISP0_DAT10__GPIO4_IO31  | MUX_PAD_CTRL(SPI_PAD_CTRL),
177 };
178 #endif
179
180 iomux_v3_cfg_t const ecspi4_pads[] = {
181         MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
182         MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
183         MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
184         MX6_PAD_EIM_D20__GPIO3_IO20  | MUX_PAD_CTRL(NO_PAD_CTRL),
185 };
186
187 int board_spi_cs_gpio(unsigned bus, unsigned cs)
188 {
189         return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
190                 ? (IMX_GPIO_NR(3, 20)) : -1;
191 }
192
193 static void setup_spi(void)
194 {
195 #ifdef CONFIG_TARGET_ZC5202
196         gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
197         gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
198         gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
199         gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
200         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
201 #endif
202
203         gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
204         gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
205         imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
206
207         enable_spi_clk(true, 3);
208 }
209 #endif
210
211 static struct i2c_pads_info i2c_pad_info1 = {
212         .scl = {
213                 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
214                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
215                 .gp = IMX_GPIO_NR(2, 30)
216         },
217         .sda = {
218                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
219                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
220                 .gp = IMX_GPIO_NR(4, 13)
221         }
222 };
223
224 static struct i2c_pads_info i2c_pad_info2 = {
225         .scl = {
226                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
227                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
228                 .gp = IMX_GPIO_NR(1, 5)
229         },
230         .sda = {
231                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
232                 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
233                 .gp = IMX_GPIO_NR(7, 11)
234         }
235 };
236
237 iomux_v3_cfg_t const usdhc2_pads[] = {
238         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
239         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
240         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
241         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
242         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
243         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
244         MX6_PAD_GPIO_4__SD2_CD_B        | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
245 };
246
247 iomux_v3_cfg_t const usdhc4_pads[] = {
248         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
249         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
250         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
251         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
252         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
253         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
254         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
255         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
256         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
257         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
258 };
259
260 #ifdef CONFIG_FSL_ESDHC_IMX
261 struct fsl_esdhc_cfg usdhc_cfg[2] = {
262         {USDHC2_BASE_ADDR},
263         {USDHC4_BASE_ADDR},
264 };
265
266 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
267
268 int board_mmc_getcd(struct mmc *mmc)
269 {
270         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
271         int ret = 0;
272
273         switch (cfg->esdhc_base) {
274         case USDHC2_BASE_ADDR:
275                 ret = !gpio_get_value(USDHC2_CD_GPIO);
276                 break;
277         case USDHC4_BASE_ADDR:
278                 ret = 1; /* eMMC/uSDHC4 is always present */
279                 break;
280         }
281
282         return ret;
283 }
284
285 int board_mmc_init(bd_t *bis)
286 {
287 #ifndef CONFIG_SPL_BUILD
288         int ret;
289         int i;
290
291         /*
292          * According to the board_mmc_init() the following map is done:
293          * (U-boot device node)    (Physical Port)
294          * mmc0                    SD2
295          * mmc1                    SD3
296          * mmc2                    eMMC
297          */
298         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
299                 switch (i) {
300                 case 0:
301                         imx_iomux_v3_setup_multiple_pads(
302                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
303                         gpio_direction_input(USDHC2_CD_GPIO);
304                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
305                         break;
306                 case 1:
307                         imx_iomux_v3_setup_multiple_pads(
308                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
309                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
310                         break;
311                 default:
312                         printf("Warning: you configured more USDHC controllers"
313                                "(%d) then supported by the board (%d)\n",
314                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
315                         return -EINVAL;
316                 }
317
318                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
319                 if (ret)
320                         return ret;
321         }
322
323         return 0;
324 #else
325         struct src *psrc = (struct src *)SRC_BASE_ADDR;
326         unsigned reg = readl(&psrc->sbmr1) >> 11;
327
328         /*
329          * Upon reading BOOT_CFG register the following map is done:
330          * Bit 11 and 12 of BOOT_CFG register can determine the current
331          * mmc port
332          * 0x1                  SD1
333          * 0x2                  SD2
334          * 0x3                  SD4
335          */
336
337         switch (reg & 0x3) {
338         case 0x1:
339                 imx_iomux_v3_setup_multiple_pads(
340                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
341                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
342                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
343                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
344                 break;
345         case 0x3:
346                 imx_iomux_v3_setup_multiple_pads(
347                         usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
348                 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
349                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
350                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
351                 break;
352         }
353
354         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
355 #endif
356
357 }
358 #endif
359
360
361 /*
362  * Do not overwrite the console
363  * Use always serial for U-Boot console
364  */
365 int overwrite_console(void)
366 {
367         return 1;
368 }
369
370 int board_eth_init(bd_t *bis)
371 {
372         setup_iomux_enet();
373         enable_enet_clk(1);
374
375         return cpu_eth_init(bis);
376 }
377
378 int board_early_init_f(void)
379 {
380
381         setup_iomux_uart();
382         setup_spi();
383
384         return 0;
385 }
386
387 int board_init(void)
388 {
389         /* address of boot parameters */
390         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
391
392         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
393         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
394
395         return 0;
396 }
397
398 int power_init_board(void)
399 {
400         struct pmic *p;
401         int ret;
402         unsigned int reg;
403
404         ret = power_pfuze100_init(I2C_PMIC);
405         if (ret)
406                 return ret;
407
408         p = pmic_get("PFUZE100");
409         ret = pmic_probe(p);
410         if (ret)
411                 return ret;
412
413         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
414         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
415
416         /* Increase VGEN3 from 2.5 to 2.8V */
417         pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
418         reg &= ~LDO_VOL_MASK;
419         reg |= LDOB_2_80V;
420         pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
421
422         /* Increase VGEN5 from 2.8 to 3V */
423         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
424         reg &= ~LDO_VOL_MASK;
425         reg |= LDOB_3_00V;
426         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
427
428         /* Set SW1AB stanby volage to 0.975V */
429         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
430         reg &= ~SW1x_STBY_MASK;
431         reg |= SW1x_0_975V;
432         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
433
434         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
435         pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
436         reg &= ~SW1xCONF_DVSSPEED_MASK;
437         reg |= SW1xCONF_DVSSPEED_4US;
438         pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
439
440         /* Set SW1C standby voltage to 0.975V */
441         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
442         reg &= ~SW1x_STBY_MASK;
443         reg |= SW1x_0_975V;
444         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
445
446         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
447         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
448         reg &= ~SW1xCONF_DVSSPEED_MASK;
449         reg |= SW1xCONF_DVSSPEED_4US;
450         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
451
452         return 0;
453 }
454
455 #ifdef CONFIG_CMD_BMODE
456 static const struct boot_mode board_boot_modes[] = {
457         /* 4 bit bus width */
458         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
459         /* 8 bit bus width */
460         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
461         {NULL,   0},
462 };
463 #endif
464
465 int board_late_init(void)
466 {
467 #ifdef CONFIG_CMD_BMODE
468         add_board_boot_modes(board_boot_modes);
469 #endif
470
471         env_set("board_name", BOARD_NAME);
472         return 0;
473 }
474
475 int checkboard(void)
476 {
477         puts("Board: ");
478         puts(BOARD_NAME "\n");
479
480         return 0;
481 }
482
483 #ifdef CONFIG_SPL_BUILD
484 #include <spl.h>
485 #include <linux/libfdt.h>
486
487 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
488         .dram_sdclk_0 =  0x00020030,
489         .dram_sdclk_1 =  0x00020030,
490         .dram_cas =  0x00020030,
491         .dram_ras =  0x00020030,
492         .dram_reset =  0x00020030,
493         .dram_sdcke0 =  0x00003000,
494         .dram_sdcke1 =  0x00003000,
495         .dram_sdba2 =  0x00000000,
496         .dram_sdodt0 =  0x00003030,
497         .dram_sdodt1 =  0x00003030,
498         .dram_sdqs0 =  0x00000030,
499         .dram_sdqs1 =  0x00000030,
500         .dram_sdqs2 =  0x00000030,
501         .dram_sdqs3 =  0x00000030,
502         .dram_sdqs4 =  0x00000030,
503         .dram_sdqs5 =  0x00000030,
504         .dram_sdqs6 =  0x00000030,
505         .dram_sdqs7 =  0x00000030,
506         .dram_dqm0 =  0x00020030,
507         .dram_dqm1 =  0x00020030,
508         .dram_dqm2 =  0x00020030,
509         .dram_dqm3 =  0x00020030,
510         .dram_dqm4 =  0x00020030,
511         .dram_dqm5 =  0x00020030,
512         .dram_dqm6 =  0x00020030,
513         .dram_dqm7 =  0x00020030,
514 };
515
516 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
517         .grp_ddr_type =  0x000C0000,
518         .grp_ddrmode_ctl =  0x00020000,
519         .grp_ddrpke =  0x00000000,
520         .grp_addds =  0x00000030,
521         .grp_ctlds =  0x00000030,
522         .grp_ddrmode =  0x00020000,
523         .grp_b0ds =  0x00000030,
524         .grp_b1ds =  0x00000030,
525         .grp_b2ds =  0x00000030,
526         .grp_b3ds =  0x00000030,
527         .grp_b4ds =  0x00000030,
528         .grp_b5ds =  0x00000030,
529         .grp_b6ds =  0x00000030,
530         .grp_b7ds =  0x00000030,
531 };
532
533 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
534         .p0_mpwldectrl0 =  0x001F001F,
535         .p0_mpwldectrl1 =  0x001F001F,
536         .p1_mpwldectrl0 =  0x00440044,
537         .p1_mpwldectrl1 =  0x00440044,
538         .p0_mpdgctrl0 =  0x434B0350,
539         .p0_mpdgctrl1 =  0x034C0359,
540         .p1_mpdgctrl0 =  0x434B0350,
541         .p1_mpdgctrl1 =  0x03650348,
542         .p0_mprddlctl =  0x4436383B,
543         .p1_mprddlctl =  0x39393341,
544         .p0_mpwrdlctl =  0x35373933,
545         .p1_mpwrdlctl =  0x48254A36,
546 };
547
548 /* MT41K128M16JT-125 */
549 static struct mx6_ddr3_cfg mem_ddr = {
550         .mem_speed = 1600,
551         .density = 2,
552         .width = 16,
553         .banks = 8,
554         .rowaddr = 14,
555         .coladdr = 10,
556         .pagesz = 2,
557         .trcd = 1375,
558         .trcmin = 4875,
559         .trasmin = 3500,
560 };
561
562 static void ccgr_init(void)
563 {
564         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
565
566         writel(0x00C03F3F, &ccm->CCGR0);
567         writel(0x0030FC03, &ccm->CCGR1);
568         writel(0x0FFFC000, &ccm->CCGR2);
569         writel(0x3FF00000, &ccm->CCGR3);
570         writel(0x00FFF300, &ccm->CCGR4);
571         writel(0x0F0000C3, &ccm->CCGR5);
572         writel(0x000003FF, &ccm->CCGR6);
573 }
574
575 /*
576  * This section requires the differentiation between iMX6 Sabre boards, but
577  * for now, it will configure only for the mx6q variant.
578  */
579 static void spl_dram_init(void)
580 {
581         struct mx6_ddr_sysinfo sysinfo = {
582                 /* width of data bus:0=16,1=32,2=64 */
583                 .dsize = 2,
584                 /* config for full 4GB range so that get_mem_size() works */
585                 .cs_density = 32, /* 32Gb per CS */
586                 /* single chip select */
587                 .ncs = 1,
588                 .cs1_mirror = 0,
589                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
590                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
591                 .walat = 1,     /* Write additional latency */
592                 .ralat = 5,     /* Read additional latency */
593                 .mif3_mode = 3, /* Command prediction working mode */
594                 .bi_on = 1,     /* Bank interleaving enabled */
595                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
596                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
597                 .ddr_type = DDR_TYPE_DDR3,
598                 .refsel = 1,    /* Refresh cycles at 32KHz */
599                 .refr = 7,      /* 8 refresh commands per refresh cycle */
600         };
601
602         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
603         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
604 }
605
606 void board_init_f(ulong dummy)
607 {
608         /* setup AIPS and disable watchdog */
609         arch_cpu_init();
610
611         ccgr_init();
612         gpr_init();
613
614         /* iomux and setup of i2c */
615         board_early_init_f();
616
617         /* setup GP timer */
618         timer_init();
619
620         /* UART clocks enabled and gd valid - init serial console */
621         preloader_console_init();
622
623         /* DDR initialization */
624         spl_dram_init();
625
626         /* Clear the BSS. */
627         memset(__bss_start, 0, __bss_end - __bss_start);
628
629         /* load/boot image from boot device */
630         board_init_r(NULL, 0);
631 }
632
633 #endif