board/efikamx/efikamx.c

   1 /*
   2  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   3  *
   4  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/mx5x_pins.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/gpio.h>
  31 #include <asm/errno.h>
  32 #include <asm/arch/sys_proto.h>
  33 #include <asm/arch/crm_regs.h>
  34 #include <i2c.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc.h>
  37 #include <fsl_pmic.h>
  38 #include <mc13892.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /*
  43  * Compile-time error checking
  44  */
  45 #ifndef CONFIG_MXC_SPI
  46 #error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
  47 #endif
  48
  49 /*
  50  * Shared variables / local defines
  51  */
  52 /* LED */
  53 #define EFIKAMX_LED_BLUE        0x1
  54 #define EFIKAMX_LED_GREEN       0x2
  55 #define EFIKAMX_LED_RED         0x4
  56
  57 void efikamx_toggle_led(uint32_t mask);
  58
  59 /* Board revisions */
  60 #define EFIKAMX_BOARD_REV_11    0x1
  61 #define EFIKAMX_BOARD_REV_12    0x2
  62 #define EFIKAMX_BOARD_REV_13    0x3
  63 #define EFIKAMX_BOARD_REV_14    0x4
  64
  65 /*
  66  * Board identification
  67  */
  68 u32 get_efika_rev(void)
  69 {
  70         u32 rev = 0;
  71         /*
  72          * Retrieve board ID:
  73          *      rev1.1: 1,1,1
  74          *      rev1.2: 1,1,0
  75          *      rev1.3: 1,0,1
  76          *      rev1.4: 1,0,0
  77          */
  78         mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
  79         /* set to 1 in order to get correct value on board rev1.1 */
  80         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
  81
  82         mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
  83         mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
  84         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
  85         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
  86
  87         mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
  88         mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
  89         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
  90         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
  91
  92         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
  93         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
  94         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
  95         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
  96
  97         return (~rev & 0x7) + 1;
  98 }
  99
 100 u32 get_board_rev(void)
 101 {
 102         return get_cpu_rev() | (get_efika_rev() << 8);
 103 }
 104
 105 /*
 106  * DRAM initialization
 107  */
 108 int dram_init(void)
 109 {
 110         /* dram_init must store complete ramsize in gd->ram_size */
 111         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 112                                 PHYS_SDRAM_1_SIZE);
 113         return 0;
 114 }
 115
 116 /*
 117  * UART configuration
 118  */
 119 static void setup_iomux_uart(void)
 120 {
 121         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 122                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
 123
 124         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
 125         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
 126         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
 127         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
 128         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
 129         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
 130         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
 131         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
 132 }
 133
 134 /*
 135  * SPI configuration
 136  */
 137 #ifdef CONFIG_MXC_SPI
 138 static void setup_iomux_spi(void)
 139 {
 140         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 141         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 142         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
 143                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 144
 145         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 146         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 147         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
 148                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 149
 150         /* Configure SS0 as a GPIO */
 151         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
 152         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
 153
 154         /* Configure SS1 as a GPIO */
 155         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
 156         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
 157
 158         /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
 159         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
 160         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
 161                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 162
 163         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 164         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 165         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
 166                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 167 }
 168 #else
 169 static inline void setup_iomux_spi(void) { }
 170 #endif
 171
 172 /*
 173  * PMIC configuration
 174  */
 175 #ifdef CONFIG_MXC_SPI
 176 static void power_init(void)
 177 {
 178         unsigned int val;
 179         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 180
 181         /* Write needed to Power Gate 2 register */
 182         val = pmic_reg_read(REG_POWER_MISC);
 183         val &= ~PWGT2SPIEN;
 184         pmic_reg_write(REG_POWER_MISC, val);
 185
 186         /* Externally powered */
 187         val = pmic_reg_read(REG_CHARGE);
 188         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
 189         pmic_reg_write(REG_CHARGE, val);
 190
 191         /* power up the system first */
 192         pmic_reg_write(REG_POWER_MISC, PWUP);
 193
 194         /* Set core voltage to 1.1V */
 195         val = pmic_reg_read(REG_SW_0);
 196         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
 197         pmic_reg_write(REG_SW_0, val);
 198
 199         /* Setup VCC (SW2) to 1.25 */
 200         val = pmic_reg_read(REG_SW_1);
 201         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 202         pmic_reg_write(REG_SW_1, val);
 203
 204         /* Setup 1V2_DIG1 (SW3) to 1.25 */
 205         val = pmic_reg_read(REG_SW_2);
 206         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 207         pmic_reg_write(REG_SW_2, val);
 208         udelay(50);
 209
 210         /* Raise the core frequency to 800MHz */
 211         writel(0x0, &mxc_ccm->cacrr);
 212
 213         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
 214         /* Setup the switcher mode for SW1 & SW2*/
 215         val = pmic_reg_read(REG_SW_4);
 216         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 217                 (SWMODE_MASK << SWMODE2_SHIFT)));
 218         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 219                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 220         pmic_reg_write(REG_SW_4, val);
 221
 222         /* Setup the switcher mode for SW3 & SW4 */
 223         val = pmic_reg_read(REG_SW_5);
 224         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 225                 (SWMODE_MASK << SWMODE4_SHIFT)));
 226         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 227                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
 228         pmic_reg_write(REG_SW_5, val);
 229
 230         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
 231         val = pmic_reg_read(REG_SETTING_0);
 232         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 233         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
 234         pmic_reg_write(REG_SETTING_0, val);
 235
 236         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 237         val = pmic_reg_read(REG_SETTING_1);
 238         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 239         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
 240         pmic_reg_write(REG_SETTING_1, val);
 241
 242         /* Configure VGEN3 and VCAM regulators to use external PNP */
 243         val = VGEN3CONFIG | VCAMCONFIG;
 244         pmic_reg_write(REG_MODE_1, val);
 245         udelay(200);
 246
 247         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 248         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 249                 VVIDEOEN | VAUDIOEN  | VSDEN;
 250         pmic_reg_write(REG_MODE_1, val);
 251
 252         val = pmic_reg_read(REG_POWER_CTL2);
 253         val |= WDIRESET;
 254         pmic_reg_write(REG_POWER_CTL2, val);
 255
 256         udelay(2500);
 257 }
 258 #else
 259 static inline void power_init(void) { }
 260 #endif
 261
 262 /*
 263  * MMC configuration
 264  */
 265 #ifdef CONFIG_FSL_ESDHC
 266 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 267         {MMC_SDHC1_BASE_ADDR, 1},
 268         {MMC_SDHC2_BASE_ADDR, 1},
 269 };
 270
 271 int board_mmc_getcd(u8 *absent, struct mmc *mmc)
 272 {
 273         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 274
 275         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 276                 *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
 277         else
 278                 *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
 279
 280         return 0;
 281 }
 282 int board_mmc_init(bd_t *bis)
 283 {
 284         int ret;
 285
 286         /* SDHC1 is used on all revisions, setup control pins first */
 287         mxc_request_iomux(MX51_PIN_GPIO1_0,
 288                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 289         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
 290                 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 291                 PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
 292                 PAD_CTL_ODE_OPENDRAIN_NONE |
 293                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 294         mxc_request_iomux(MX51_PIN_GPIO1_1,
 295                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 296         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 297                 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 298                 PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
 299                 PAD_CTL_SRE_FAST);
 300
 301         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
 302         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
 303
 304         /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
 305         if (get_efika_rev() < EFIKAMX_BOARD_REV_12) {
 306                 /* SDHC1 IOMUX */
 307                 mxc_request_iomux(MX51_PIN_SD1_CMD,
 308                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 309                 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 310                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 311                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 312
 313                 mxc_request_iomux(MX51_PIN_SD1_CLK,
 314                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 315                 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 316                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 317                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 318
 319                 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
 320                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 321                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 322                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 323
 324                 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
 325                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 326                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 327                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 328
 329                 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
 330                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 331                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 332                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 333
 334                 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
 335                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 336                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 337                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 338
 339                 /* SDHC2 IOMUX */
 340                 mxc_request_iomux(MX51_PIN_SD2_CMD,
 341                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 342                 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
 343                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 344
 345                 mxc_request_iomux(MX51_PIN_SD2_CLK,
 346                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 347                 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
 348                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 349
 350                 mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
 351                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
 352                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 353
 354                 mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
 355                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
 356                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 357
 358                 mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
 359                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
 360                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 361
 362                 mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
 363                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
 364                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 365
 366                 /* SDHC2 Control lines IOMUX */
 367                 mxc_request_iomux(MX51_PIN_GPIO1_7,
 368                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 369                 mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
 370                         PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 371                         PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
 372                         PAD_CTL_ODE_OPENDRAIN_NONE |
 373                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 374                 mxc_request_iomux(MX51_PIN_GPIO1_8,
 375                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 376                 mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
 377                         PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 378                         PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
 379                         PAD_CTL_SRE_FAST);
 380
 381                 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
 382                 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));
 383
 384                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 385                 if (!ret)
 386                         ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
 387         } else {        /* New boards use only SDHC1 */
 388                 /* SDHC1 IOMUX */
 389                 mxc_request_iomux(MX51_PIN_SD1_CMD,
 390                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 391                 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 392                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 393
 394                 mxc_request_iomux(MX51_PIN_SD1_CLK,
 395                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 396                 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 397                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 398
 399                 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
 400                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 401                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 402
 403                 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
 404                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 405                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 406
 407                 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
 408                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 409                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 410
 411                 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
 412                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 413                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 414
 415                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 416         }
 417         return ret;
 418 }
 419 #endif
 420
 421 /*
 422  * ATA
 423  */
 424 #ifdef  CONFIG_MX51_PATA
 425 #define ATA_PAD_CONFIG  (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
 426 void setup_iomux_ata(void)
 427 {
 428         mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
 429         mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
 430         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
 431         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
 432         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
 433         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
 434         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
 435         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
 436         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
 437         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
 438         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
 439         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
 440         mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
 441         mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
 442         mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
 443         mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
 444         mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
 445         mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
 446         mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
 447         mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
 448         mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
 449         mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
 450         mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
 451         mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
 452         mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
 453         mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
 454         mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
 455         mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
 456         mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
 457         mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
 458         mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
 459         mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
 460         mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
 461         mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
 462         mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
 463         mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
 464         mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
 465         mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
 466         mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
 467         mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
 468         mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
 469         mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
 470         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
 471         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
 472         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
 473         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
 474         mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
 475         mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
 476         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
 477         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
 478         mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
 479         mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
 480         mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
 481         mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
 482         mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
 483         mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
 484         mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
 485         mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
 486 }
 487 #else
 488 static inline void setup_iomux_ata(void) { }
 489 #endif
 490
 491 /*
 492  * LED configuration
 493  */
 494 void setup_iomux_led(void)
 495 {
 496         /* Blue LED */
 497         mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
 498         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);
 499
 500         /* Green LED */
 501         mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
 502         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);
 503
 504         /* Red LED */
 505         mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
 506         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);
 507 }
 508
 509 void efikamx_toggle_led(uint32_t mask)
 510 {
 511         gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
 512                         mask & EFIKAMX_LED_BLUE);
 513         gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
 514                         mask & EFIKAMX_LED_GREEN);
 515         gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
 516                         mask & EFIKAMX_LED_RED);
 517 }
 518
 519 /*
 520  * Board initialization
 521  */
 522 static void init_drive_strength(void)
 523 {
 524         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
 525         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
 526         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
 527         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
 528         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
 529         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
 530         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
 531         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
 532                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 533         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
 534                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 535         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
 536         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
 537         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
 538         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
 539         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
 540         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
 541         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
 542         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
 543         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
 544         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
 545         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
 546         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
 547         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
 548         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
 549         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
 550         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
 551
 552         /* Setting pad options */
 553         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
 554                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 555                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 556         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
 557                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 558                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 559         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
 560                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 561                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 562         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
 563                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 564                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 565         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
 566                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 567                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 568         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
 569                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 570                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 571         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
 572                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 573                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 574         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
 575                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 576                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 577         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
 578                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 579                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 580         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
 581                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 582                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 583         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
 584                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 585                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 586         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
 587                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 588                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 589         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
 590                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 591                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 592         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
 593                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 594                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 595 }
 596
 597 int board_early_init_f(void)
 598 {
 599         init_drive_strength();
 600
 601         setup_iomux_uart();
 602         setup_iomux_spi();
 603         setup_iomux_led();
 604
 605         return 0;
 606 }
 607
 608 int board_init(void)
 609 {
 610         gd->bd->bi_arch_number = MACH_TYPE_MX51_EFIKAMX;
 611         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 612
 613         return 0;
 614 }
 615
 616 int board_late_init(void)
 617 {
 618         setup_iomux_spi();
 619
 620         power_init();
 621
 622         setup_iomux_led();
 623         setup_iomux_ata();
 624
 625         efikamx_toggle_led(EFIKAMX_LED_BLUE);
 626
 627         return 0;
 628 }
 629
 630 int checkboard(void)
 631 {
 632         puts("Board: Efika MX\n");
 633
 634         return 0;
 635 }