1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
10 #include <asm/arch/stm32.h>
11 #include <asm/arch/sys_proto.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
21 #include <env_internal.h>
23 #include <generic-phy.h>
26 #include <i2c_eeprom.h>
35 #include <linux/delay.h>
36 #include <power/regulator.h>
37 #include <remoteproc.h>
41 #include <usb/dwc2_udc.h>
44 /* SYSCFG registers */
45 #define SYSCFG_BOOTR 0x00
46 #define SYSCFG_PMCSETR 0x04
47 #define SYSCFG_IOCTRLSETR 0x18
48 #define SYSCFG_ICNR 0x1C
49 #define SYSCFG_CMPCR 0x20
50 #define SYSCFG_CMPENSETR 0x24
51 #define SYSCFG_PMCCLRR 0x44
53 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
54 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
56 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
57 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
58 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
59 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
60 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
62 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
63 #define SYSCFG_CMPCR_READY BIT(8)
65 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
67 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
68 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
70 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
72 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
73 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
74 #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
75 #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
78 * Get a global data pointer
80 DECLARE_GLOBAL_DATA_PTR;
82 int setup_mac_address(void)
84 unsigned char enetaddr[6];
88 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
89 if (ret) /* ethaddr is already set */
92 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
94 printf("%s: No eeprom0 path offset\n", __func__);
98 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
100 printf("Cannot find EEPROM!\n");
104 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
106 printf("Error reading configuration EEPROM!\n");
110 if (is_valid_ethaddr(enetaddr))
111 eth_env_set_enetaddr("ethaddr", enetaddr);
119 const char *fdt_compat;
122 if (IS_ENABLED(CONFIG_TFABOOT))
127 printf("Board: stm32mp1 in %s mode", mode);
128 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
130 if (fdt_compat && fdt_compat_len)
131 printf(" (%s)", fdt_compat);
137 #ifdef CONFIG_BOARD_EARLY_INIT_F
138 static u8 brdcode __section("data");
139 static u8 ddr3code __section("data");
140 static u8 somcode __section("data");
142 static void board_get_coding_straps(void)
144 struct gpio_desc gpio[4];
148 node = ofnode_path("/config");
149 if (!ofnode_valid(node)) {
150 printf("%s: no /config node?\n", __func__);
158 ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
159 gpio, ARRAY_SIZE(gpio),
161 for (i = 0; i < ret; i++)
162 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
164 ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
165 gpio, ARRAY_SIZE(gpio),
167 for (i = 0; i < ret; i++)
168 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
170 ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
171 gpio, ARRAY_SIZE(gpio),
173 for (i = 0; i < ret; i++)
174 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
176 printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
177 somcode, ddr3code, brdcode);
180 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
184 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
188 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
192 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
198 int board_early_init_f(void)
200 board_get_coding_straps();
205 #ifdef CONFIG_SPL_LOAD_FIT
206 int board_fit_config_name_match(const char *name)
210 snprintf(test, sizeof(test), "somrev%d_boardrev%d", somcode, brdcode);
212 if (!strcmp(name, test))
220 static void board_key_check(void)
222 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
224 struct gpio_desc gpio;
225 enum forced_boot_mode boot_mode = BOOT_NORMAL;
227 node = ofnode_path("/config");
228 if (!ofnode_valid(node)) {
229 debug("%s: no /config node?\n", __func__);
232 #ifdef CONFIG_FASTBOOT
233 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
234 &gpio, GPIOD_IS_IN)) {
235 debug("%s: could not find a /config/st,fastboot-gpios\n",
238 if (dm_gpio_get_value(&gpio)) {
239 puts("Fastboot key pressed, ");
240 boot_mode = BOOT_FASTBOOT;
243 dm_gpio_free(NULL, &gpio);
246 #ifdef CONFIG_CMD_STM32PROG
247 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
248 &gpio, GPIOD_IS_IN)) {
249 debug("%s: could not find a /config/st,stm32prog-gpios\n",
252 if (dm_gpio_get_value(&gpio)) {
253 puts("STM32Programmer key pressed, ");
254 boot_mode = BOOT_STM32PROG;
256 dm_gpio_free(NULL, &gpio);
260 if (boot_mode != BOOT_NORMAL) {
261 puts("entering download mode...\n");
262 clrsetbits_le32(TAMP_BOOT_CONTEXT,
263 TAMP_BOOT_FORCED_MASK,
269 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
271 #include <usb/dwc2_udc.h>
272 int g_dnl_board_usb_cable_connected(void)
274 struct udevice *dwc2_udc_otg;
277 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
278 DM_GET_DRIVER(dwc2_udc_otg),
281 debug("dwc2_udc_otg init failed\n");
283 return dwc2_udc_B_session_valid(dwc2_udc_otg);
286 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
287 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
289 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
291 if (!strcmp(name, "usb_dnl_dfu"))
292 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
293 else if (!strcmp(name, "usb_dnl_fastboot"))
294 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
297 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
302 #endif /* CONFIG_USB_GADGET */
305 static int get_led(struct udevice **dev, char *led_string)
310 led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
312 pr_debug("%s: could not find %s config string\n",
313 __func__, led_string);
316 ret = led_get_by_label(led_name, dev);
318 debug("%s: get=%d\n", __func__, ret);
325 static int setup_led(enum led_state_t cmd)
330 ret = get_led(&dev, "u-boot,boot-led");
334 ret = led_set_state(dev, cmd);
339 static void __maybe_unused led_error_blink(u32 nb_blink)
351 ret = get_led(&led, "u-boot,error-led");
353 /* make u-boot,error-led blinking */
354 /* if U32_MAX and 125ms interval, for 17.02 years */
355 for (i = 0; i < 2 * nb_blink; i++) {
356 led_set_state(led, LEDST_TOGGLE);
363 /* infinite: the boot process must be stopped */
364 if (nb_blink == U32_MAX)
368 static void sysconf_init(void)
370 #ifndef CONFIG_TFABOOT
372 #ifdef CONFIG_DM_REGULATOR
373 struct udevice *pwr_dev;
374 struct udevice *pwr_reg;
381 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
383 /* interconnect update : select master using the port 1 */
386 /* today information is hardcoded in U-Boot */
387 writel(BIT(9), syscfg + SYSCFG_ICNR);
389 /* disable Pull-Down for boot pin connected to VDD */
390 bootr = readl(syscfg + SYSCFG_BOOTR);
391 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
392 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
393 writel(bootr, syscfg + SYSCFG_BOOTR);
395 #ifdef CONFIG_DM_REGULATOR
396 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
397 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
398 * The customer will have to disable this for low frequencies
399 * or if AFMUX is selected but the function not used, typically for
400 * TRACE. Otherwise, impact on power consumption.
403 * enabling High Speed mode while VDD>2.7V
404 * with the OTP product_below_2v5 (OTP 18, BIT 13)
405 * erroneously set to 1 can damage the IC!
406 * => U-Boot set the register only if VDD < 2.7V (in DT)
407 * but this value need to be consistent with board design
409 ret = uclass_get_device_by_driver(UCLASS_PMIC,
410 DM_GET_DRIVER(stm32mp_pwr_pmic),
413 ret = uclass_get_device_by_driver(UCLASS_MISC,
414 DM_GET_DRIVER(stm32mp_bsec),
417 pr_err("Can't find stm32mp_bsec driver\n");
421 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
425 /* get VDD = vdd-supply */
426 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
429 /* check if VDD is Low Voltage */
431 if (regulator_get_value(pwr_reg) < 2700000) {
432 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
433 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
434 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
435 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
436 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
437 syscfg + SYSCFG_IOCTRLSETR);
440 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
443 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
446 debug("VDD unknown");
451 /* activate automatic I/O compensation
452 * warning: need to ensure CSI enabled and ready in clock driver
454 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
456 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
458 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
462 static void board_init_fmc2(void)
464 #define STM32_FMC2_BCR1 0x0
465 #define STM32_FMC2_BTR1 0x4
466 #define STM32_FMC2_BWTR1 0x104
467 #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
468 #define STM32_FMC2_BCRx_FMCEN BIT(31)
469 #define STM32_FMC2_BCRx_WREN BIT(12)
470 #define STM32_FMC2_BCRx_RSVD BIT(7)
471 #define STM32_FMC2_BCRx_FACCEN BIT(6)
472 #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
473 #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
474 #define STM32_FMC2_BCRx_MUXEN BIT(1)
475 #define STM32_FMC2_BCRx_MBKEN BIT(0)
476 #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
477 #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
478 #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
479 #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
480 #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
481 #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
483 #define RCC_MP_AHB6RSTCLRR 0x218
484 #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
485 #define RCC_MP_AHB6ENSETR 0x19c
486 #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
488 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
489 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
490 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
491 STM32_FMC2_BCRx_MBKEN;
492 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
493 STM32_FMC2_BTRx_BUSTURN(2) |
494 STM32_FMC2_BTRx_DATAST(0x22) |
495 STM32_FMC2_BTRx_ADDHLD(2) |
496 STM32_FMC2_BTRx_ADDSET(2);
498 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
499 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
500 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
502 /* KS8851-16MLL -- Muxed mode */
503 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
504 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
505 /* AS7C34098 SRAM on X11 -- Muxed mode */
506 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
507 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
509 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
512 /* board dependent setup after realloc */
517 /* address of boot parameters */
518 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
520 /* probe all PINCTRL for hog */
521 for (uclass_first_device(UCLASS_PINCTRL, &dev);
523 uclass_next_device(&dev)) {
524 pr_debug("probe pincontrol = %s\n", dev->name);
529 #ifdef CONFIG_DM_REGULATOR
530 regulators_enable_boot_on(_DEBUG);
537 if (CONFIG_IS_ENABLED(LED))
543 int board_late_init(void)
546 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
547 const void *fdt_compat;
550 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
552 if (fdt_compat && fdt_compat_len) {
553 if (strncmp(fdt_compat, "st,", 3) != 0)
554 env_set("board_name", fdt_compat);
556 env_set("board_name", fdt_compat + 3);
560 /* Check the boot-source to disable bootdelay */
561 boot_device = env_get("boot_device");
562 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
563 env_set("bootdelay", "0");
565 #ifdef CONFIG_BOARD_EARLY_INIT_F
566 env_set_ulong("dh_som_rev", somcode);
567 env_set_ulong("dh_board_rev", brdcode);
568 env_set_ulong("dh_ddr3_code", ddr3code);
574 void board_quiesce_devices(void)
577 setup_led(LEDST_OFF);
581 /* eth init function : weak called in eqos driver */
582 int board_interface_eth_init(struct udevice *dev,
583 phy_interface_t interface_type)
587 bool eth_clk_sel_reg = false;
588 bool eth_ref_clk_sel_reg = false;
590 /* Gigabit Ethernet 125MHz clock selection. */
591 eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
593 /* Ethernet 50Mhz RMII clock selection */
594 eth_ref_clk_sel_reg =
595 dev_read_bool(dev, "st,eth_ref_clk_sel");
597 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
602 switch (interface_type) {
603 case PHY_INTERFACE_MODE_MII:
604 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
605 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
606 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
608 case PHY_INTERFACE_MODE_GMII:
610 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
611 SYSCFG_PMCSETR_ETH_CLK_SEL;
613 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
614 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
616 case PHY_INTERFACE_MODE_RMII:
617 if (eth_ref_clk_sel_reg)
618 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
619 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
621 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
622 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
624 case PHY_INTERFACE_MODE_RGMII:
625 case PHY_INTERFACE_MODE_RGMII_ID:
626 case PHY_INTERFACE_MODE_RGMII_RXID:
627 case PHY_INTERFACE_MODE_RGMII_TXID:
629 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
630 SYSCFG_PMCSETR_ETH_CLK_SEL;
632 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
633 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
636 debug("%s: Do not manage %d interface\n",
637 __func__, interface_type);
638 /* Do not manage others interfaces */
642 /* clear and set ETH configuration bits */
643 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
644 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
645 syscfg + SYSCFG_PMCCLRR);
646 writel(value, syscfg + SYSCFG_PMCSETR);
651 enum env_location env_get_location(enum env_operation op, int prio)
656 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
657 return ENVL_SPI_FLASH;
663 #if defined(CONFIG_OF_BOARD_SETUP)
664 int ft_board_setup(void *blob, bd_t *bd)
670 static void board_copro_image_process(ulong fw_image, size_t fw_size)
672 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
674 if (!rproc_is_initialized())
676 printf("Remote Processor %d initialization failed\n",
681 ret = rproc_load(id, fw_image, fw_size);
682 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
683 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
687 env_set("copro_state", "booted");
691 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);